三星HBM 4的底气

Core Viewpoint - Samsung Electronics is confident in its leading position in the sixth-generation HBM4 (High Bandwidth Memory) market, which is crucial for AI infrastructure, due to its advanced core technology and the ability to meet NVIDIA's peak performance requirements [1][2]. Summary by Sections HBM4 Development and Production - Samsung has increased the size of its Core Die 1c (10nm) DRAM chips to enhance the stability of both DRAM and HBM4, although this decision negatively impacts profitability by reducing the number of chips produced per wafer [1]. - The yield rate for 1c DRAM is currently around 60%, prompting industry insiders to suggest that Samsung should upgrade its technology promptly [1]. - HBM4 is expected to be commercially available this year and will be fully utilized in NVIDIA's latest AI accelerator, the Rubin chip, featuring a doubled I/O port count of 2048 compared to the previous generation, significantly enhancing performance [1]. Performance Standards and Confidence - NVIDIA has urged memory suppliers to improve HBM4 performance standards, raising the initial JEDEC standard from 8 Gbps to 11.7 Gbps [2]. - Samsung's confidence in HBM4 commercialization stems from its commitment to exceed JEDEC standards from the outset, ensuring stable yields and industry-leading performance without redesigns [2]. Technical Challenges and Innovations - Concerns were initially raised about Samsung's yield stability compared to competitors like SK Hynix and Micron, which use the same core chip as HBM3E [3]. - Samsung's breakthrough involves increasing the size of its 1c DRAM chips while maintaining core circuit line widths, which simplifies mass production and improves yield rates, estimated to be between 50% and 60% as of this month [3]. TSV Technology and Manufacturing Stability - The enlarged chip size is believed to enhance the stability of the TSV (Through-Silicon Via) process, crucial for HBM manufacturing, as HBM4 requires more TSV holes due to the increased I/O count [4]. - Samsung's 1c DRAM provides greater flexibility in TSV layout, reducing density and improving heat dissipation and reliability [4]. Profitability Concerns - Critics argue that Samsung's HBM4 profitability is lacking compared to competitors, as the larger chip size reduces wafer yield, and the current yield rates are expected to be lower than those of competitors using the same core chip as HBM3E [5]. - The use of TC-NCF (Thermal Compression Non-Conductive Film) packaging technology for stacking DRAM may fundamentally lower yield rates [5].