突破1纳米！北大团队取得重要芯片突破

Core Viewpoint - The research team at Peking University has developed the smallest and lowest power-consuming ferroelectric transistor, which is expected to support the enhancement of AI chip computing power and energy efficiency [2][3]. Group 1: Ferroelectric Transistor Development - The physical gate length of the ferroelectric transistor has been reduced to the limit of 1 nanometer, achieving atomic-scale precision [8]. - This advancement allows for the formation of a high-strength electric field within the ferroelectric layer, requiring only a minimal external energy of 0.6V to easily flip the ferroelectric polarization [8]. - The new design significantly reduces energy consumption, achieving a level that is an order of magnitude lower than the best international standards [8]. Group 2: Advantages Over Traditional Transistors - Unlike traditional semiconductor logic transistors, ferroelectric transistors (FeFET) integrate both storage and computing capabilities, potentially breaking the efficiency bottleneck caused by the separation of storage and computation in traditional architectures [3]. - The "storage-computation integration" capability of ferroelectric transistors aligns with the evolutionary direction of AI chips, making them a promising new foundational device for neuromorphic computing [3]. Group 3: Technical Innovations - The research team has addressed the high energy consumption and voltage mismatch issues that have limited the large-scale application of traditional ferroelectric transistors by utilizing a nanogate structure design [3][5]. - The nanogate design acts like a "lever amplification" of the electric field, enabling polarization reversal of the ferroelectric material at very low voltage costs, thus achieving a breakthrough in energy consumption reduction [5].