混合键合，延期？

Core Viewpoint - JEDEC is discussing the relaxation of height standards for High Bandwidth Memory (HBM), which is crucial for the performance of AI-related semiconductors, allowing for more DRAM stacking without the need for next-generation equipment [1][3]. Group 1: HBM Height Standards - HBM is structured with multiple layers of DRAM, and increasing the number of layers enhances processing capability and performance, but is limited by height standards set by the semiconductor industry [1][3]. - Current mainstream production is 12-layer HBM, while 16-layer and higher versions are still in the R&D phase. The height of HBM4, which began mass production this year, is 775 micrometers [3][4]. - JEDEC is considering raising the height limit to 900 micrometers, which could allow for more layers without needing advanced hybrid bonding machines [3][4]. Group 2: Impact on Semiconductor Manufacturers - If height specifications are significantly relaxed, the introduction of hybrid bonding machines may be delayed, benefiting companies like Hanmi Semiconductor, which leads the TC bonding machine market with a 71.2% share [4][6]. - The strategic adjustments of HBM manufacturers are anticipated, as maintaining existing manufacturing processes can lower costs and improve yield rates [6][7]. - The eventual adoption of hybrid bonding technology is seen as inevitable due to its potential to enhance data transfer efficiency and energy efficiency, especially for 20-layer and above HBM chips [6][7]. Group 3: Customer Demand and Market Dynamics - Major customers like NVIDIA are driving the demand for higher performance, which may accelerate the rollout of hybrid bonding technology if their requirements significantly exceed current capabilities [7]. - The timing for the widespread adoption of hybrid bonding machines will depend on changes in standards, technological advancements, and customer demands [7].