Group 1 - Cadence announced the successful tape-out of its third-generation UCIe IP solution using TSMC's N3P advanced process, achieving a channel bandwidth of 64Gbps [1] - UCIe is a universal interconnect specification suitable for high-speed interconnects between chiplets, available in two versions: standard packaging and advanced packaging [3] - Cadence's IP achieves an edge bandwidth density of 3.6Tbps/mm in standard packaging and can reach 21.08Tbps/mm in advanced packaging [3] Group 2 - The 64Gbps UCIe IP is optimized for AI and HPC applications, supporting protocols such as AXI, CXS, CHI-C2C, PCIe, and CXL.io, allowing seamless integration with high-speed PHY [3]