Intel(US:INTC) Hua Er Jie Jian Wen·2025-06-02 13:52Core Viewpoint - Intel has made significant advancements in chip packaging technology under the leadership of new CEO Chen Liwu, particularly with the introduction of the EMIB-T technology, which enhances chip packaging size and power delivery capabilities to support new technologies like HBM4/4e [1][9]. Group 1: EMIB-T Technology Advancements - EMIB-T integrates TSV (Through-Silicon Via) for vertical signal transmission between chips, reducing power transmission resistance by over 30%, which minimizes voltage drop and signal noise [2][6]. - The technology incorporates high-density MIM (Metal-Insulator-Metal) capacitors to suppress power noise, ensuring signal integrity, especially in high-performance applications like AI accelerators and data center processors [2][7]. - EMIB-T supports a maximum package size of 120x180 mm, allowing integration of over 38 bridges and 12 dies, with plans to reduce bump pitch from 45 microns to as low as 25 microns in the future [2][7]. Group 2: Strategic Importance and Market Position - Intel's foundry aims to leverage cutting-edge process node technologies to manufacture chips for both internal and external clients, enhancing performance, cost, and energy efficiency through complex heterogeneous designs [4][5]. - The EMIB-T technology is crucial for supporting HBM4 memory and UCIe interconnect requirements, making it an ideal packaging solution for AI accelerators, data center processors, and supercomputing chips [7][8]. - Intel plans to achieve mass production of EMIB-T packaging by the second half of 2025, with a vision to integrate over 24 HBM chips in a single package by 2028, significantly impacting global semiconductor packaging technology [9].