“A+H”持续升温！又一家千亿市值存储企业赴港上市

Core Viewpoint - The storage industry is facing both opportunities and challenges this year, with leading companies finding it relatively easy to secure financing, while a wave of mergers and acquisitions and capacity battles are imminent [1]. Group 1: Company Strategy and Goals - The company, Changqi Technology, plans to issue H-shares and list on the Hong Kong Stock Exchange to enhance its international strategy, attract talent, and improve overseas financing capabilities [2][4]. - The strategic goal for the next five to ten years is to become a leading international full interconnect chip design company, focusing on high-performance interconnect solutions for cloud computing and AI infrastructure [4]. Group 2: Financial Performance - In Q1 2025, the sales revenue from interconnect chip products reached 1.139 billion yuan, a year-on-year increase of 63.92% and a quarter-on-quarter increase of 17.19%, marking eight consecutive quarters of growth [4]. - For 2024, the company reported a revenue of 3.639 billion yuan, up 59.2%, and a net profit of 1.412 billion yuan, up 213.1% [5]. - The company anticipates that the order amount for interconnect chips to be delivered in Q2 2025 will exceed 1.29 billion yuan, driven by the demand for DDR5 memory interface chips and high-performance interconnect chips [5]. Group 3: Market Trends and Projections - The global memory interface chip market is projected to grow from 1.009 billion USD in 2024 to 1.268 billion USD in 2025, with a CAGR of 28.5% from 2025 to 2031 [5]. - By 2028, the global storage interface chip market is expected to reach 19.475 billion yuan, with the Chinese market projected to exceed 100 billion yuan in the same year [6]. Group 4: Competitive Position - Changqi Technology holds a 43.35% market share in the memory interface chip market as of 2023, having established itself as a leader in the design and development of memory interface chips [6]. - The company has successfully positioned itself in the DDR4 and DDR5 generations, leading the formulation of international standards for DDR5 interface chips [6].