TSMC(US:TSM) Zhi Tong Cai Jing·2025-07-03 15:09Core Insights - Morgan Stanley reports that TSMC has initiated the construction of a 310mm Panel-Level chiplet advanced packaging pilot line, marking the beginning of a significant transformation in the advanced packaging industry [1][2] - The CoPoS (Chip-on-Panel-on-Substrate) system aims to address capacity bottlenecks and cost issues in the CoWoS (Chip-on-Wafer-on-Substrate) process, particularly for next-generation AI training and inference GPUs and ASICs [1][3] Industry Developments - TSMC's investment in the CoPoS 310mm pilot line coincides with ASE's announcement of a 300mm panel 2.3D packaging technology, indicating a rapid transition in the advanced packaging sector [2] - The semiconductor industry anticipates large-scale delivery and installation of CoPoS-related equipment by mid-2026, with process ramp-up expected in 2027 [2] Technical Advancements - CoPoS leverages silicon interposer technology from CoWoS but makes systematic adjustments in substrate form, high-end semiconductor equipment, and yield bottlenecks, aiming for enhanced performance and scalability [2][4] - The CoPoS process allows for a higher number of chiplets and HBM stacks in a single package, significantly increasing bandwidth and capacity compared to existing CoWoS solutions [3][8] Market Implications - Major AI and HPC clients like NVIDIA and AMD stand to benefit from CoPoS, which alleviates supply constraints and reduces manufacturing costs [3] - The transition to CoPoS is expected to drive substantial growth across the semiconductor supply chain, particularly for high-end equipment manufacturers [5] Future Outlook - The CoPoS system is projected to enable a peak bandwidth of over 13-15TB/s, with storage capacity potentially doubling, thus meeting the surging demand for AI computational power [8] - As AI model parameters continue to grow, CoPoS will leverage its panel area advantages to enhance AI chip performance and reduce unit cost of computation [8]