TSMC(US:TSM) Hua Er Jie Jian Wen·2025-07-16 03:26Core Viewpoint - TSMC's CoPoS packaging technology mass production is likely delayed until 2029-2030, which may force NVIDIA to adjust its chip design strategy towards alternative architectures [1][2][3] Group 1: TSMC's CoPoS Technology Delay - TSMC's CoPoS technology, originally scheduled for mass production in 2027, is now expected to be delayed until the second half of 2029 due to technical challenges [2][3] - Key challenges include managing differences between panels and wafers, controlling warpage over larger areas, and addressing more redistribution layers (RDL) [2] Group 2: Impact on NVIDIA's Product Strategy - NVIDIA's Rubin Ultra GPU, initially requiring up to eight wafer-sized CoWoS-L interconnects, may need to shift to a multi-chip module (MCM) architecture due to the CoPoS delay [3] - This adjustment is similar to Amazon's Trainium 2 design, which utilizes CoWoS-R and MCM to integrate computing chips and HBM on a single substrate [3] Group 3: TSMC's Capital Expenditure Adjustments - TSMC's capital expenditure for the latter half of 2026 may increasingly focus on wafer-level multi-chip modules (WMCM) and system-on-chip (SoIC) technologies due to the CoPoS delay [4][5] - The report maintains forecasts for TSMC's CoWoS capacity, expecting monthly wafer production to reach 70,000 and 90,000-100,000 by the end of 2025 and 2026, respectively [4]