TSMC(US:TSM) Sou Hu Cai Jing·2026-01-06 12:12Core Viewpoint - TSMC's U.S. factory is projected to achieve profitability in the second half of 2025, but recent data reveals significant cost disparities compared to its Taiwan operations, raising concerns about the sustainability of this investment [2][4]. Cost Analysis - TSMC's Fab 18 in Taiwan has a capital expenditure of $27 billion, while Fab 21 in the U.S. has a capital expenditure of $14.38 billion [3]. - The total cost per wafer in Taiwan is $6,681, yielding a gross margin of 62%, whereas in the U.S., the total cost per wafer is $16,123, resulting in a gross margin of only 8% [3][24]. - Depreciation costs per wafer are significantly higher in the U.S. at $10,200 compared to $2,100 in Taiwan, primarily due to lower capacity utilization in the U.S. factory [6][24]. Labor Costs - Labor costs per wafer in the U.S. are $3,600, double that of Taiwan's $1,800, exacerbated by cultural differences affecting operational efficiency [8][10]. - U.S. labor regulations limit overtime, impacting productivity, with U.S. factories experiencing an average of 40 minutes more downtime per day compared to Taiwan [10][12]. Strategic Decisions - TSMC's decision to build in the U.S. is influenced by a $52 billion government subsidy, which comes with conditions that restrict expansion in other countries and mandate R&D spending in the U.S. [14][24]. - Major clients like Apple and Nvidia are pushing for supply chain diversification, with Apple already committing to using U.S.-produced wafers despite higher costs [16][18]. Long-term Outlook - TSMC's U.S. expansion is viewed as a strategic gamble, with potential long-term benefits as the global semiconductor industry undergoes significant geopolitical restructuring [20][24]. - By 2027, TSMC aims to increase local supply chain integration to 60%, and analysts predict that overall gross margins could exceed 60% by 2026, although U.S. operations may drag margins down by 2% to 3% [22][24]. - The shift towards regional supply chains is seen as a necessary evolution in the semiconductor industry, balancing efficiency with resilience [24][26].