IBM全新芯片设计与架构

Core Viewpoint - IBM has announced a new quantum computing architecture that significantly reduces the number of qubits required for error correction, supporting its goal to build a large-scale fault-tolerant quantum computer named "Starling" by 2029 [4][6]. Summary by Sections Quantum Error Correction - Quantum computers rely on qubits, which have inherent unreliability, making error correction essential for building reliable large-scale quantum devices. Error correction techniques create "logical qubits" by distributing information across multiple physical qubits for redundancy [4]. - The most common error correction method, "surface code," requires about 1000 physical qubits to form one logical qubit. IBM initially focused on this method but later recognized the engineering challenges involved [4][5]. New Error Correction Scheme - In 2019, IBM began exploring alternatives and introduced a new error correction scheme called quantum low-density parity-check (qLDPC) code, which requires approximately one-tenth the number of qubits compared to surface code [5][6]. Upcoming Developments - IBM plans to launch a processor named "Loon" later this year, which will feature couplers that connect distant qubits on the same chip, crucial for implementing the qLDPC code. This non-local interaction enhances efficiency compared to surface code [7]. - Following "Loon," IBM aims to release a processor called "Kookaburra" in 2026, which will include both logical processing units and quantum memory, marking the first demonstration of the foundational modules needed for subsequent systems [7]. Starling and Future Roadmap - The Starling quantum computer is expected to be built by 2028 and connected to the cloud the following year. It will be located in a new quantum data center in Poughkeepsie, New York, and will serve as a foundation for a future system, codenamed Blue Jay, with 2000 logical qubits [8]. - IBM's new architecture represents a significant breakthrough, with enhanced interconnectivity and support from advancements in 3D manufacturing. Achieving 200 logical qubits could propel quantum computing into practical problem-solving [8]. Engineering Challenges - One of the main challenges is improving the overall fidelity of gate operations, which needs to be reduced by an order of magnitude for the new architecture to succeed. Enhancing the coherence time of qubits is a key path forward [8][10]. - IBM has achieved an average coherence time of 2 milliseconds in isolated test devices, but translating this to large chips remains challenging. Recent progress on the Heron chip has increased coherence time from approximately 150 microseconds to 250 microseconds [9]. Infrastructure and Component Reduction - Significant engineering challenges remain in infrastructure support, including connectors and amplifiers. However, the new architecture's reduced qubit requirements also decrease the number of necessary components, which is a major advantage of the qLDPC codes [10].