台积电正在开发第二代“SoW”

Core Viewpoint - TSMC is developing the second generation of its System on Wafer (SoW) technology, which integrates various components onto a large 300mm silicon wafer, enhancing performance and efficiency in semiconductor packaging [1][2]. Group 1: SoW Technology Overview - The SoW technology integrates chiplets, stacked chip modules, memory modules, power modules, I/O boards, and heat dissipation boards on both sides of a 300mm wafer [1]. - The first generation of SoW, named SoW-P, focuses on integrating System on Chip (SoC) as the main circuit, while the second generation, SoW-X, will combine SoC with High Bandwidth Memory (HBM) for heterogeneous integration [2]. Group 2: CoWoS Technology - The second generation of SoW is an upgrade of the CoWoS (Chip on Wafer on Substrate) technology, which uses an intermediate substrate to enhance data transmission speed and density [7]. - CoWoS technology has evolved since its introduction in 2012, with significant advancements in the size and efficiency of silicon interposers, particularly after 2016 [8][9]. Group 3: Future Developments and Roadmap - TSMC's roadmap includes expanding the size of the intermediate substrate in CoWoS technology, with plans for a substrate size 5.5 times larger than the photomask by 2025-2026 and 8 times larger by 2026-2027 [13]. - The SoW-X technology is expected to be implemented by 2027, with anticipated challenges related to high manufacturing costs and customer acceptance [24]. Group 4: Performance Metrics - The SoW-X module, arranged in a 4x4 matrix, is designed to achieve a performance per watt that is 65% higher than a PCIe cluster system, although it is 27% lower than a single CoWoS-L module [20]. - The total power consumption for SoW-X is projected to reach 17kW, with water cooling solutions being considered for heat dissipation [22].