EMPYREAN(SZ:301269) 半导体行业观察·2025-08-14 01:28Core Viewpoint - The introduction of Argus by Huada Jiutian has revolutionized the physical verification process in chip design, transforming it from a bottleneck into an accelerator for project delivery, significantly enhancing verification speed and team collaboration efficiency [1][3][13]. Group 1: Verification Speed and Efficiency - Argus utilizes a powerful distributed computing engine that can leverage thousands of CPU cores, completing full-chip DRC checks in just a few hours, compared to traditional methods that could take days [3][4]. - For large-scale SoC DRC checks, Argus reduces the time for Base Layer checks from 19.3 hours to 15 hours, saving 4.3 hours, and achieves a speedup of over three times for Latch up and Voltage checks, cutting down from 36 hours to under 11 hours [3][4]. - Full Chip checks that typically require 712 CPU cores and take up to 4 days can be completed by Argus in just 24.6 hours, saving at least 3 days [3]. Group 2: Result Analysis and Collaboration - Argus provides a user-friendly PVE result visualization platform that allows for easy identification and analysis of DRC errors, significantly reducing the time spent on error filtering [7][11]. - The platform enables real-time collaboration among multiple roles in a project, allowing for efficient distribution and management of DRC errors, which can number in the thousands [9][10]. - Features such as incremental comparison and multi-DB integration allow teams to focus on new issues while managing multiple results databases seamlessly, enhancing overall project efficiency [12][11]. Group 3: Impact on Workflow - The ability to receive complete DRC/LVS results on the same day as submission allows teams to address issues promptly, eliminating the need for overnight work and improving iterative verification processes [9][10]. - Argus maximizes hardware utilization by enabling thousands of CPU cores to operate simultaneously, instilling confidence in timely project completion [9][10]. - The platform's capabilities transform engineers from mere report readers into data analysts, allowing them to focus on critical issues that impact chip yield and reliability [12][11].