AMD，盯上了互联

Core Insights - AMD is planning significant improvements in its Zen 6 processors through the implementation of D2D (die-to-die) interconnect technology, which has already been observed in the Strix Halo APU [1][4] - The current D2D communication method relies on SERDES PHYs, which convert parallel data streams into serial bit streams, leading to inefficiencies in energy consumption and increased latency [3][6] - The Strix Halo APU introduces a new communication method that utilizes TSMC's InFO-oS and a re-distribution layer (RDL) to enhance bandwidth and reduce power consumption and latency [5][7] Existing Interconnect Mechanism - AMD employs SERDES PHYs at the edges of CCDs for die-to-die communication, allowing high-speed serial channels to communicate across organic substrates [3] - The SERDES method incurs overhead due to serialization/deserialization processes, consuming energy and adding latency to D2D communication [3] New Method in Strix Halo - The Strix Halo APU features a redesigned communication approach for Zen 6 chiplets, utilizing short parallel wires in the RDL to eliminate the overhead associated with data flow conversion [5] - High Yield discovered a rectangular array of small solder pads in Strix Halo, indicating the implementation of Fan-Out technology and the removal of large SERDES modules [5] Improvements and Challenges of the New Method - The new Fan-Out method reduces power and latency requirements by eliminating the need for serialization/deserialization, while overall bandwidth can be increased by adding more ports on the CPU Fabric [7] - However, the complexity of multi-layer RDL design increases the difficulty of implementation, and the space occupied by Fan-Out wiring necessitates adjustments in wiring priorities [7]