HBM 4，新标准

Core Viewpoint - The semiconductor industry is developing a new type of High Bandwidth Memory (HBM) called SPHBM4, which aims to reduce design complexity and manufacturing costs while maintaining performance similar to existing HBM products. This development could significantly impact companies like Samsung Electronics and SK Hynix, as well as the broader ecosystem including TSMC and NVIDIA [3][6]. Group 1: SPHBM4 Development - JEDEC is in the final stages of developing the SPHBM4 standard, which utilizes the same DRAM as HBM4 but serializes I/O pins at a 4:1 ratio, reducing the number of I/O pins from 1024 to 512 while still supporting the same bandwidth [3][4]. - The SPHBM4 standard is expected to be released in the coming months, according to Eliyan, a U.S. semiconductor startup that supports the new standard [4][5]. Group 2: Technical Aspects - SPHBM4's performance relies on stable interconnect technology that can achieve over four times the transmission speed per I/O pin, which is crucial for its operation [4]. - The introduction of SPHBM4 will necessitate a redesign of the substrate chip responsible for memory controller functions, as the I/O pin count will be significantly reduced [5]. Group 3: Packaging and Cost Implications - The intermediary layer, which connects HBM and the printed circuit board (PCB), can simplify connections due to the reduced number of I/O pins, allowing for the use of organic intermediary layers instead of more expensive silicon layers [5]. - The adoption of organic intermediary layers is expected to lower packaging manufacturing costs while allowing for more flexible designs, potentially increasing overall storage capacity [5]. Group 4: Market Uncertainty - The commercialization of SPHBM4 remains uncertain, as the standard is still under development and may undergo changes or even be rejected by the JEDEC board [6]. - Major tech companies are currently focused on enhancing both the speed and density of HBM, indicating that SPHBM4 may be one of several attempts to reduce manufacturing costs for AI accelerators based on HBM technology [6].