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神经符号学习框架(CMO)
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芯片设计效率提升2.5倍,中科大华为诺亚联合,用GNN+蒙特卡洛树搜索优化电路设计 | ICLR2025
量子位· 2025-04-09 08:58
Core Viewpoint - The article discusses the significance of Logic Optimization (LO) in chip design and introduces a novel data-driven framework called Circuit Symbolic Learning Framework (CMO) that enhances the efficiency of traditional logic optimization methods by up to 2.5 times [2][4][34]. Group 1: Introduction and Background - Chip design automation (EDA) is crucial in the semiconductor industry, with Logic Optimization being a key EDA tool aimed at improving chip quality by reducing circuit size and depth [5][7]. - Logic Optimization is an NP-hard problem, and existing heuristic algorithms face challenges due to ineffective and redundant transformations, leading to time-consuming optimization processes [8][12]. Group 2: Proposed Solution - The research team developed CMO, a data-driven framework that utilizes a teacher-student paradigm, combining Graph Neural Networks (GNN) and Monte Carlo Tree Search (MCTS) to create efficient symbolic scoring functions [6][30]. - CMO significantly improves the efficiency of key logic optimization operators, achieving a maximum speedup of 2.5 times, allowing tasks that previously took 10 minutes to be completed in just 4 minutes [4][34]. Group 3: Experimental Results - The CMO framework demonstrated substantial efficiency improvements, with traditional logic optimization operators like Mfs2 seeing their runtime reduced from 78,784 seconds to 32,001 seconds, a reduction of approximately 59.4% [34]. - The optimization quality also improved, with the maximum reduction in circuit depth reaching 30.23%, exemplified by the Hyp circuit where depth decreased from 8,259 layers to 5,762 layers, significantly lowering circuit latency [34][35].