Leveraging years of stacked BSI sensor production, Tower’s wafer-scale 3D-IC technology unlocks integration of SiPho and EIC processes for emerging applications such as Co-Packaged Optics, including full support by Cadence design tools to the stacked platform technology Migdal Haemek, Israel – November 12, 2025 – Tower Semiconductor (NASDAQ/TASE: TSEM), a leading foundry of high-value analog semiconductor solutions, today announced the expansion of its existing, mature 300mm wafer bonding technology, origi ...

Core Insights - Tower Semiconductor has expanded its 300mm wafer bonding technology to enable heterogeneous 3D-IC integration across Silicon Photonics (SiPho) and SiGe BiCMOS processes, addressing the demand for compact, high-performance systems in data center applications [1][2][3] Group 1: Technology Advancements - The new wafer-scale 3D-IC technology allows for the stacking of different process technologies, integrating application-specific functions into a single high-density chip, enhancing functionality and performance [2][3] - Tower's collaboration with Cadence Design Systems has resulted in an enhanced design flow that supports co-simulation and co-verification of multiple process technologies, improving design efficiency for customers [3][4] Group 2: Market Applications - The technology supports emerging applications such as Co-Packaged Optics (CPO), which require compact and high-performance integration of Photonic ICs (PICs) and Electronic ICs (EICs) [2][3] - Tower's advancements in 3D integration are positioned to meet the growing market demand for innovative solutions in various sectors, including consumer, industrial, automotive, and medical [6][7] Group 3: Company Positioning - Tower Semiconductor is recognized as a leading foundry for high-value analog semiconductor solutions, focusing on sustainable partnerships and innovative technology offerings [6][7] - The company operates multiple facilities globally, enhancing its capacity to meet customer needs and support multi-fab sourcing [7]