Core Insights - STMicroelectronics is advancing its next-generation Panel-Level Packaging (PLP) technology with a new pilot line in Tours, France, expected to be operational in Q3 2026 [2][3] - The PLP technology aims to enhance manufacturing efficiency and reduce costs, enabling the production of smaller, more powerful electronic devices [3][4] - A capital investment of over $60 million has been allocated for the development of the new PLP pilot line, which is part of a broader initiative to reshape the company's manufacturing footprint [5][8] Technology Development - PLP technology utilizes large-area carriers instead of traditional circular wafers, allowing for higher manufacturing throughput and cost efficiency [3][7] - The new PLP pilot line will focus on Direct Copper Interconnect (DCI), which improves electrical connectivity and reduces power losses compared to traditional methods [10][11] - The initiative is part of a strategic focus on heterogeneous integration, which aims to enhance the capabilities of various product lines, including RF, analog, power, and microcontrollers [4][8] Operational Impact - The Tours site will leverage synergies with the local R&D ecosystem, including the CERTEM R&D center, to support advanced manufacturing infrastructure [5][8] - STMicroelectronics has demonstrated its capability in high-performing chip packaging and testing in Europe, with a current production volume exceeding 5 million units per day using a highly automated line [9]