Core Insights - The article emphasizes the growing demand for computing power driven by generative AI, highlighting the challenges faced by traditional architectures and the potential of RISC-V combined with DSA as a key player in AI acceleration [1][4]. Group 1: Event Overview - The 2025 Andes RISC-V CON in Beijing will feature a roundtable forum discussing the advantages and challenges of RISC-V in AI computing acceleration, bringing together academic and industry experts [1]. - The event is scheduled for August 27, 2025, from 9:00 AM to 5:30 PM at the Lijing Huayuan Hotel in Beijing [8]. Group 2: Key Discussion Topics - The combination of RISC-V and DSA is explored for its ability to provide flexibility and scalability in AI computing, enabling customized acceleration solutions for various application scenarios [4]. - The forum will address multi-layer optimization from Graph to Kernel, discussing the roles of compiler ecosystems and RVV/RVM extensions in overcoming performance bottlenecks at both operator and system levels [4]. - Practical applications of RISC-V in low-power edge AI and high-performance data center AI will be analyzed, focusing on balancing power consumption, real-time performance, and overall efficiency [4]. Group 3: Featured Speakers and Demonstrations - Notable speakers include Andes CEO Lin Zhiming and technical experts who will discuss how RISC-V can accelerate application deployment in chip design, along with innovations in AI, embedded security, and next-generation automotive chips [8]. - Partner companies such as PUFsecurity, S2C, and Siemens will showcase the latest RISC-V products and live demonstrations [9]. - Andes will demonstrate the performance and application potential of its DeepSeek and Android running on the Andes Qilai Platform, which features a 64-bit AX45MP and NX27V vector processor [10].