Software Enhancement - Vivado Design Suite 2025.1% introduces Pblock locking feature to prevent accidental movement in the GUI [1] - The "Lock Pblocks" icon, when enabled, secures Pblocks, preventing unintended relocation during navigation [2] - This feature addresses the issue where mouse clicks within a selected Pblock would move it instead of zooming [3] - With the Pblocks locked, zoom actions within a selected Pblock will perform as expected, improving navigation [4] - Users can unlock Pblocks by deselecting the "Lock Pblocks" icon to enable movement again [4][5]

Versal Adaptive SoC Transceiver Overview - Versal 自适应 SoC 平台集成了高性能收发器，为各种应用提供灵活性和可扩展性 [1] - AMD 的 FPGA 和自适应 SoC 产品组合中广泛使用千兆位收发器 [2] - AMD Versal 自适应 SoC 利用 GTM、GTY 和 GTYP 收发器来满足不同的应用需求 [3] - GTYP 变体支持 PCIe Gen5 [4] - GTM 58G PAM4 收发器针对最新的铜缆、背板和光接口进行了调整，配置后组合两个通道时支持 112G [4] Debugging and Optimization Tools - 集成误码率测试仪 (IBERT) 是一种强大的工具，用于 AMD Serial IO 接口的系统内验证和调试 [6] - AMD Vivado Serial Analyzer 提供 GT 链路分组，简化了收发器链路的分析 [12] - AMD Vivado Serial Analyzer 提供了一个用户友好的界面，用于选择 PRBS 模式，确保全面的测试和验证 [15] - 2D 眼图扫描通过显示收发器链路的眼图来可视化信号完整性 [16] - 1D Bathtub Plots 提供链路裕量和性能的图形表示 [18]

SHEL Flow Overview - AMD's Software Hardware Exchange Loop (SHEL) flow facilitates hardware and software configuration data exchange among open-source and proprietary tools [2][3] - SHEL decouples hardware and software, ensuring synchronization across components like hardware, firmware, software, and operating systems [4] - SHEL translates AMD proprietary XSA into open-source hardware descriptions, allowing integration into existing processes [5] - SHEL enables industry standards like Yocto Project, Xen, OpenAMP, and Zephyr [6] Technical Implementation - The process starts with an XSA file from an AMD Vivado project, extracting the system device tree using SDTGen [6] - SDTGen translates proprietary output from AMD Vivado Design Suite into a stable, open-source format [7] - Gen-machine-conf processes device tree data into Linux build and configuration information within a Yocto Project environment [8] - A custom Linux OS is created based on the system device tree, using a prebuilt template BSP YAML file for VEK385 [21] - Bitbake recipes are run inside the Yocto Project to generate final products, including a boot bin and EDF Linux SD card image [28] Customization and Integration - Users can integrate AMD tools into their existing processes by using open-source hardware descriptions [5] - Customizations can be made to the OS by modifying the local conf file [25] - The gen-machine-conf command with a template parameter of the edited YAML file generates custom Linux build and configuration information [24]

Product Focus - AMD Vivado Design Suite is optimized for AMD Spartan UltraScale+ FPGA family [1] - The tutorial guides users through project creation to implementation using Vivado tool [1] - A real design is built and demonstrated to highlight best practices and performance benefits [1] Target Audience - The tutorial is tailored for both beginner and experienced FPGA developers [1] Resources and Legal - Additional information can be found at AMD's website [1] - Trademarks belong to Advanced Micro Devices, Inc [1]

Product & Technology - AMD MicroBlaze V soft processor is used in the Vivado Design Suite [1] - The design targets the Spartan UltraScale+ FPGA family [1] - The tutorial covers the MicroBlaze V flow and implements it in a Vivado project [1] - An XSA hardware design file is generated for software integration [1] Target Audience & Application - The tutorial provides a guided walkthrough for adding processing power to Spartan UltraScale+ devices [1] - It aims to streamline FPGA development [1] Resources & Legal - More information can be found at AMD's website [1] - The content is copyrighted by Advanced Micro Devices, Inc in 2025 [1]

Key Features of Unified Selective Device Installer (USDI) - AMD Vivado 2025.1 introduces the Unified Selective Device Installer (USDI) for efficient FPGA and SoC design [1][3] - USDI allows users to download only necessary device files, streamlining installation and workflow [3] - USDI consolidates Vivado, Vitis, and related tools into a single installer with selective device file downloads [4] - The Filter Device section streamlines device selection by allowing users to search by device name or series [6] - Users can select specific devices within a series, further reducing download size and enabling tailored selection [8] Benefits of USDI - USDI reduces download size and disk space usage by up to 60% [4][11] - Installation times are faster, and valuable disk space is saved, improving setup efficiency and system performance [6] - Tailoring the install speeds up the process, optimizes storage, and saves bandwidth [5] Specific Device Support and Examples - Selective installation currently applies to AMD Versal devices, allowing users to choose specific parts [4] - Downloading all devices from the Versal AI Edge Series in AMD Vivado 2024.2 required approximately 83 GB download size and 212 GB disk space [5] - With USDI, selecting all devices from the Versal AI Edge Series reduces the download size to 22 GB and disk space to 77 GB, a 60% reduction in download size [5] Offline Installation - USDI allows users to select specific devices for offline installation by downloading an image from the Web Installer [9] - Users can select "Download Image (Install Separately)" from the web installer setup and choose the required Versal devices [10]

Overview of Advanced Flow - AMD Vivado Design Suite 2024.2 introduces Advanced Flow for Versal devices, featuring new place and route algorithms for faster design performance and improved routability [5] - Advanced Flow aims to reduce compile times for larger, more complex AMD Versal adaptive SoCs, offering up to 2X speedup for Versal SSIT devices and 1.7X for Versal monolithic devices [9] - The Advanced Flow is integrated into the Vivado IDE, maintaining familiar design processes and Tcl scripting [8] Key Features and Architecture - Advanced Flow includes automatic partitioning to divide large designs into smaller problems solvable in parallel, along with new infrastructure for efficient parallel compilation [10] - The new architecture uses leaner data structures for storage and retrieval of physical design information, improving place and route speed, checkpoint handling, and memory footprint [10][11] - A new timing engine optimized for the placer's data structures helps quickly evaluate the timing impact of placement changes [11] - The placer reduces routing congestion, and the clock region placer's capacity is increased for better handling of complex designs with many global clocks [12] Directives and Subdirectives - The Advanced Flow simplifies placer directives to five basic options: Quick, RuntimeOptimized, Default, Explore, and AggressiveExplore [18] - A new placer option, Subdirective, provides finer-grained control over different phases of placement, allowing multiple subdirectives to be applied simultaneously [20] - Subdirectives unlock more combinations and allow exploration of different options at each placer phase, covering more solution space than original directive options [25] Implementation and Migration - AMD recommends a methodical approach to timing closure, starting with Default, Explore, and AggressiveExplore strategies, then combining the best directive with key subdirectives [32][33] - Migrating to Advanced Flow requires archiving the project, as the migration is not reversible and resets runs and options to Advanced Flow place and route [37] - Projects from pre-2024.2 Vivado versions cannot reuse place and route data in Advanced Flow due to a new database structure [41]

Overview of Segmented Configuration - The industry focuses on faster software boot processes and updates to meet growing demands [2] - Segmented configuration is introduced as a new approach to align solutions with silicon features and boundaries, aiming for faster boot times [10][11] - The primary goal is to boot processors, memory, and OS before loading the PL, offering flexibility in PL configuration [12] Technical Details - Segmented configuration splits the booting process into two phases: PS/boot PDI and PL PDI [11][17] - PS/boot PDI configures the PS, PMC, DDR, CPM, and horizontal NoC [17] - PL PDI configures the user design, vertical NoC, transceivers, I/O, and hardened blocks in the PL [17] - The flow allows dynamic reloading of the PL configuration, enabling on-the-fly changes in the PL domain [29] Implementation and Consistency - Enabling segmented configuration in Vivado leads to a "Zynq MPSoC-like" deployment of the PL [20] - The tool requires identification of necessary NoC connectivity for the initial boot image [21] - Consistency between implementation runs is ensured by locking the NoC solution and exporting/importing it using Tcl commands [30][31] PL Reconfiguration - PL reconfiguration requires pausing activity between the PS and PL and flushing any remaining transactions from the NMU [38] - Users need to unload/load drivers as needed before or after PL reconfiguration, applying device tree overlays [39] - The PL PDI can be fetched by the software application and loaded using high-speed interfaces [40]