Hello and welcome. In this short video we will take a look at how to lock the Pblocks in place in the graphical user interface of AMD Vivado Design Suite. In Vivado Design Suite 2025.1%, we introduced the ability to lock Pblocks in place.When the Lock Pblocks icon is enabled, the Pblocks cannot be moved in the GUI. This feature prevents accidental Pblock movement while navigating or working in the device window. If you use Pblocks in your device implementations, you may have encountered the following issue: ...

Welcome to the AMD Versal Adaptive SoC Transceiver Debug Overview. In this presentation, we will explore the advanced capabilities of Versal GT transceivers, focusing on their role in high-speed data applications and the tools available for debugging and optimizing the AMD Serial IO interface. The Versal adaptive SoC is a cutting-edge platform that integrates high-performance transceivers, offering unparalleled flexibility and scalability for a wide range of applications.Let’s dive into the details of how t ...

Hello, welcome to a guide to hardware handoff using the Software Hardware Exchange Loop (SHEL) flow. This video will begin by introducing and describing the SHEL. Then, an XSA will be generated from an AMD Vivado Example design for the VEK385.Using that XSA, a system device tree will then be created. After that, the system device tree will be used to build a custom Linux build and configuration information with the gen-machine-conf command. Lastly, a boot.bin and EDF Linux disk image WIC will be created fro ...

Product Focus - AMD Vivado Design Suite is optimized for AMD Spartan UltraScale+ FPGA family [1] - The tutorial guides users through project creation to implementation using Vivado tool [1] - A real design is built and demonstrated to highlight best practices and performance benefits [1] Target Audience - The tutorial is tailored for both beginner and experienced FPGA developers [1] Resources and Legal - Additional information can be found at AMD's website [1] - Trademarks belong to Advanced Micro Devices, Inc [1]

This tutorial shows how to design with the AMD MicroBlaze™ V soft processor in the Vivado™ Design Suite, specifically targeting the Spartan™ UltraScale+™ FPGA family. We’ll cover the MicroBlaze V flow, implement it in a Vivado project, and generate an XSA hardware design file for software integration. A clear, guided walkthrough for adding processing power to Spartan UltraScale+ devices and streamlining FPGA development. Discover more: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado. ...

Key Features of Unified Selective Device Installer (USDI) - AMD Vivado 2025.1 introduces the Unified Selective Device Installer (USDI) for efficient FPGA and SoC design [1][3] - USDI allows users to download only necessary device files, streamlining installation and workflow [3] - USDI consolidates Vivado, Vitis, and related tools into a single installer with selective device file downloads [4] - The Filter Device section streamlines device selection by allowing users to search by device name or series [6] - Users can select specific devices within a series, further reducing download size and enabling tailored selection [8] Benefits of USDI - USDI reduces download size and disk space usage by up to 60% [4][11] - Installation times are faster, and valuable disk space is saved, improving setup efficiency and system performance [6] - Tailoring the install speeds up the process, optimizes storage, and saves bandwidth [5] Specific Device Support and Examples - Selective installation currently applies to AMD Versal devices, allowing users to choose specific parts [4] - Downloading all devices from the Versal AI Edge Series in AMD Vivado 2024.2 required approximately 83 GB download size and 212 GB disk space [5] - With USDI, selecting all devices from the Versal AI Edge Series reduces the download size to 22 GB and disk space to 77 GB, a 60% reduction in download size [5] Offline Installation - USDI allows users to select specific devices for offline installation by downloading an image from the Web Installer [9] - Users can select "Download Image (Install Separately)" from the web installer setup and choose the required Versal devices [10]

Overview of Advanced Flow - AMD Vivado Design Suite 2024.2 introduces Advanced Flow for Versal devices, featuring new place and route algorithms for faster design performance and improved routability [5] - Advanced Flow aims to reduce compile times for larger, more complex AMD Versal adaptive SoCs, offering up to 2X speedup for Versal SSIT devices and 1.7X for Versal monolithic devices [9] - The Advanced Flow is integrated into the Vivado IDE, maintaining familiar design processes and Tcl scripting [8] Key Features and Architecture - Advanced Flow includes automatic partitioning to divide large designs into smaller problems solvable in parallel, along with new infrastructure for efficient parallel compilation [10] - The new architecture uses leaner data structures for storage and retrieval of physical design information, improving place and route speed, checkpoint handling, and memory footprint [10][11] - A new timing engine optimized for the placer's data structures helps quickly evaluate the timing impact of placement changes [11] - The placer reduces routing congestion, and the clock region placer's capacity is increased for better handling of complex designs with many global clocks [12] Directives and Subdirectives - The Advanced Flow simplifies placer directives to five basic options: Quick, RuntimeOptimized, Default, Explore, and AggressiveExplore [18] - A new placer option, Subdirective, provides finer-grained control over different phases of placement, allowing multiple subdirectives to be applied simultaneously [20] - Subdirectives unlock more combinations and allow exploration of different options at each placer phase, covering more solution space than original directive options [25] Implementation and Migration - AMD recommends a methodical approach to timing closure, starting with Default, Explore, and AggressiveExplore strategies, then combining the best directive with key subdirectives [32][33] - Migrating to Advanced Flow requires archiving the project, as the migration is not reversible and resets runs and options to Advanced Flow place and route [37] - Projects from pre-2024.2 Vivado versions cannot reuse place and route data in Advanced Flow due to a new database structure [41]

Overview of Segmented Configuration - The industry focuses on faster software boot processes and updates to meet growing demands [2] - Segmented configuration is introduced as a new approach to align solutions with silicon features and boundaries, aiming for faster boot times [10][11] - The primary goal is to boot processors, memory, and OS before loading the PL, offering flexibility in PL configuration [12] Technical Details - Segmented configuration splits the booting process into two phases: PS/boot PDI and PL PDI [11][17] - PS/boot PDI configures the PS, PMC, DDR, CPM, and horizontal NoC [17] - PL PDI configures the user design, vertical NoC, transceivers, I/O, and hardened blocks in the PL [17] - The flow allows dynamic reloading of the PL configuration, enabling on-the-fly changes in the PL domain [29] Implementation and Consistency - Enabling segmented configuration in Vivado leads to a "Zynq MPSoC-like" deployment of the PL [20] - The tool requires identification of necessary NoC connectivity for the initial boot image [21] - Consistency between implementation runs is ensured by locking the NoC solution and exporting/importing it using Tcl commands [30][31] PL Reconfiguration - PL reconfiguration requires pausing activity between the PS and PL and flushing any remaining transactions from the NMU [38] - Users need to unload/load drivers as needed before or after PL reconfiguration, applying device tree overlays [39] - The PL PDI can be fetched by the software application and loaded using high-speed interfaces [40]