天眼查资料显示，芯原微电子（南京）有限公司，成立于2020年，位于南京市，是一家以从事软件和信 息技术服务业为主的企业。企业注册资本10000万人民币。通过天眼查大数据分析，芯原微电子（南 京）有限公司专利信息139条，此外企业还拥有行政许可3个。 芯原微电子（上海）股份有限公司，成立于2001年，位于上海市，是一家以从事软件和信息技术服务业 为主的企业。企业注册资本49991.1232万人民币。通过天眼查大数据分析，芯原微电子（上海）股份有 限公司共对外投资了20家企业，参与招投标项目68次，财产线索方面有商标信息57条，专利信息233 条，此外企业还拥有行政许可45个。 金融界2025年7月28日消息，国家知识产权局信息显示，芯原微电子（南京）有限公司、芯原微电子 （上海）股份有限公司、芯原微电子（海南）有限公司、芯原微电子（成都）有限公司、芯原科技（上 海）有限公司申请一项名为"一种处理器及数据分配方法以及电子设备"的专利，公开号 CN120380456A，申请日期为2025年03月。 专利摘要显示，本申请涉及一种处理器及数据分配方法以及电子设备。该处理器包括：集群分配器和多 个处理集群；每个处理集群包 ...

Core Insights - The fifth RISC-V China Summit will be held from July 16 to 19, 2025, in Shanghai, featuring a main forum, nine vertical sub-forums, five workshops, and a 4,500 square meter technology exhibition area, attracting hundreds of companies, research institutions, and open-source technology communities [1] - The presentation by the market director of Hanjian Software highlighted the challenges and innovations in verifying high-performance RISC-V multi-core processors, laying a solid foundation for the proliferation and development of RISC-V processors [3] Development Stages of Xiangshan Processors - The Xiangshan processor series has undergone three significant development phases: - Yanqi Lake (First Generation): Focused on architecture exploration and foundational technology, successfully implementing out-of-order execution architecture [3] - Nanhu (Second Generation): Achieved a performance leap, benchmarking against ARM Cortex-A76, recognized as a high-performance RISC-V processor core [3] - Kunming Lake (Third Generation): Targets data centers and high-performance computing, benchmarking against ARM Neoverse N2, supporting 64-core large-scale high-performance SoC system architecture [3] Key Technologies in Kunming Lake - Multi-core scalability: Architecture supports expansion from 64 to 256 cores to meet future technological demands [4] - High-speed interconnect bus: Utilizes new high-bandwidth, low-latency NoC technology for efficient data exchange [4] - Strong consistency memory system: Introduces large-scale multi-level cache and directory-based cache coherence protocols to ensure system stability [4] Challenges in Multi-core CPU Verification - The verification process faces three key challenges: - Large scale: Multi-core systems involve complex buses, multi-level caches, and peripheral interfaces, requiring FPGA resources far exceeding traditional platforms [4] - High performance requirements: Aiming for a target operating speed of 10 MHz on FPGA to support OS operation and hardware-software co-verification [4] - Debugging difficulties: Ensuring cache coherence, bus integrity, and scheduling optimization poses significant debugging challenges, with deep-rooted bugs in cross-core interactions being hard to locate [4] Verification Methodology - A systematic four-step verification methodology was proposed: - Design porting and adaptation: Automating the adaptation from ASIC to FPGA, including clock tree, storage model, and interface IP conversion [5] - Compilation and resource optimization: Balancing resource usage and efficient compilation in large-scale designs [6] - Progressive bring-up strategy: Gradually expanding from single-core to multi-core systems to reduce debugging complexity [6] - Hardware-software co-debugging technology: Utilizing hardware emulation and backdoor loading techniques for rapid fault localization and kernel loading speed breakthroughs [6] Future Directions - The Xiangshan team aims to deepen verification efficiency, explore larger-scale device cascading, and encourage EDA vendors to develop more features supporting multi-core system verification, such as low-power verification and dynamic power analysis [6][7] - The development of Xiangshan processors signifies significant progress in China's high-performance RISC-V processor field, providing replicable and scalable standardized verification methods for the industry [7]