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英伟达下一代GPU,巨幅升级!
半导体芯闻· 2025-09-29 09:45
Core Insights - NVIDIA and AMD are competing to develop superior AI architectures, with significant upgrades planned for their next-generation products in terms of power consumption, memory bandwidth, and process node utilization [1][2] - AMD's Instinct MI450 AI series is expected to be highly competitive against NVIDIA's Vera Rubin, with both companies making substantial modifications to their designs [1][5] Group 1: AMD's Optimism and Product Comparison - AMD executive Forrest Norrod expressed optimism about the MI450 product line, likening it to AMD's transformative "Milan moment" with the EPYC 7003 series [2] - Norrod stated that MI450 will be more competitive than NVIDIA's Vera Rubin and will utilize AMD's technology stack [3] - The MI450X's TGP has increased by 200W, while Rubin's TGP has risen by 500W to 2300W, indicating a significant enhancement in performance [5] Group 2: Specifications and Technological Advancements - The MI450 is rumored to launch in 2026 with HBM4 memory, offering up to 432 GB per GPU and a memory bandwidth of approximately 19.6 TB/s, while Vera Rubin is expected to have around 288 GB per GPU and a bandwidth of ~20 TB/s [6] - AMD's dense compute performance is estimated at ~40 PFLOPS, compared to ~50 PFLOPS for NVIDIA's offering [6] - Both companies are expected to narrow the technological gap as they adopt similar technologies, including HBM4 and TSMC's N3P node [6] Group 3: D2D Interconnect Technology - AMD plans to significantly enhance its D2D interconnect technology with the upcoming Zen 6 processors, as evidenced by developments in the Strix Halo APU [7][8] - The current D2D communication method using SERDES has limitations in efficiency and latency, which AMD aims to address with new designs [10][12] - The Strix Halo utilizes TSMC's InFO-oS and redistribution layer (RDL) to improve communication between chips, reducing power consumption and latency [12][14]
Imagination E系列发布:架构进步巨大,静待市场发挥
3 6 Ke· 2025-05-08 12:24
Core Insights - Imagination Technologies has released its new generation GPU IP, the Imagination E series, which significantly enhances performance and efficiency compared to previous architectures [5][21] - The E series features a modernized architecture that improves energy efficiency by 35% and reduces data transmission latency through a shorter pipeline design [6][10] - The AI architecture of the E series integrates AI units directly with traditional graphics processing units, allowing for dynamic configuration based on workload demands [17][20] Group 1: Architectural Improvements - The Imagination E series adopts a new architecture that shortens the pipeline depth of ALUs, enhancing instruction hit rates and reducing latency [6][10] - This design shift reflects a return to a more modern architecture, moving away from the long VLIW pipeline previously used by Imagination [8][10] - The architecture allows for a unified design where each USC can function as either a graphics or AI processing unit, optimizing resource usage [20] Group 2: AI Integration - Imagination's AI unit design categorizes existing GPU AI units into four levels, with the E series representing a more integrated approach [11][14] - The E series eliminates the bandwidth competition between AI and graphics tasks by allowing all USCs to switch roles as needed, thus improving efficiency [20] - This innovative design aims to reduce power consumption and hardware costs while maintaining high performance across both graphics and AI workloads [20] Group 3: Performance Metrics - The E series offers a wide range of hardware configurations, with a minimum setup providing 8 GPixel/s and 0.25 TFLOPS of 32-bit floating-point performance [21] - At maximum specifications, the E series can achieve 400 GPixel/s and 12.8 TFLOPS of 32-bit floating-point performance, positioning it competitively against existing GPUs [24] - The potential performance of the E series in mobile and desktop applications aligns with current market trends, supporting various domestic GPU development initiatives [26][29]