Core Insights - NVIDIA and AMD are competing to develop superior AI architectures, with significant upgrades planned for their next-generation products in terms of power consumption, memory bandwidth, and process node utilization [1][2] - AMD's Instinct MI450 AI series is expected to be highly competitive against NVIDIA's Vera Rubin, with both companies making substantial modifications to their designs [1][5] Group 1: AMD's Optimism and Product Comparison - AMD executive Forrest Norrod expressed optimism about the MI450 product line, likening it to AMD's transformative "Milan moment" with the EPYC 7003 series [2] - Norrod stated that MI450 will be more competitive than NVIDIA's Vera Rubin and will utilize AMD's technology stack [3] - The MI450X's TGP has increased by 200W, while Rubin's TGP has risen by 500W to 2300W, indicating a significant enhancement in performance [5] Group 2: Specifications and Technological Advancements - The MI450 is rumored to launch in 2026 with HBM4 memory, offering up to 432 GB per GPU and a memory bandwidth of approximately 19.6 TB/s, while Vera Rubin is expected to have around 288 GB per GPU and a bandwidth of ~20 TB/s [6] - AMD's dense compute performance is estimated at ~40 PFLOPS, compared to ~50 PFLOPS for NVIDIA's offering [6] - Both companies are expected to narrow the technological gap as they adopt similar technologies, including HBM4 and TSMC's N3P node [6] Group 3: D2D Interconnect Technology - AMD plans to significantly enhance its D2D interconnect technology with the upcoming Zen 6 processors, as evidenced by developments in the Strix Halo APU [7][8] - The current D2D communication method using SERDES has limitations in efficiency and latency, which AMD aims to address with new designs [10][12] - The Strix Halo utilizes TSMC's InFO-oS and redistribution layer (RDL) to improve communication between chips, reducing power consumption and latency [12][14]

如果您希望可以时常见面，欢迎标星收藏哦~ 英 特 尔 Arrow Lake 架 构 的 晶 圆 照 片 （ Die shots ） 已 被 公 布 ， 全 面 展 示 了 其 " 芯 粒"（chiplet/tile）设计的全貌。Andreas Schiling在X平台上分享了多张Arrow Lake的近距离照 片，揭示了其各个芯粒的布局以及计算芯粒内部核心的排布。 第一张照片展示了英特尔桌面版Core Ultra 200S系列CPU的完整晶圆图像：左上角是计算芯粒 （compute tile），下方是I/O芯粒（IO tile），右侧是SoC芯粒和GPU芯粒。左下和右上两个区 域是"填充芯粒"（filler dies），用于提供结构上的支撑与稳定性。 点这里加关注，锁定更多原创内容 *免责声明：文章内容系作者个人观点，半导体芯闻转载仅为了传达一种不同的观点，不代表半导体芯闻对该 观点赞同或支持，如果有任何异议，欢迎联系我们。 计算芯粒采用台积电最先进的N3B制程工艺，面积为117.241平方毫米；I/O芯粒和SoC芯粒则使 用台积电较旧的N6工艺，分别为24.475平方毫米和86.648平方毫米。所有芯粒都安 ...