Core Viewpoint - The article discusses the introduction of CMOS 2.0 by imec in 2024, which aims to address the increasing computational demands driven by diverse applications through a new paradigm of system-on-chip (SoC) design and advanced 3D interconnect technology [2][4][32]. Group 1: CMOS 2.0 Overview - CMOS 2.0 introduces a structured approach to SoC design, dividing it into functional layers optimized with the most suitable technology options based on functional constraints [2]. - The method emphasizes internal heterogeneity within the SoC, allowing for the separation of logic parts into high-drive logic layers and high-density logic layers, each tailored for specific performance and power efficiency [2][4]. Group 2: Key Technologies - A significant feature of CMOS 2.0 is the Backside Power Delivery Network (BSPDN), which powers active devices from the wafer's back, enabling high-density backend processing without voltage drop limitations [4][26]. - The implementation of advanced 3D interconnects and backside technologies is crucial for realizing the CMOS 2.0 vision, with innovations such as wafer-to-wafer hybrid bonding providing sub-micron interconnect spacing [5][10]. Group 3: Performance and Efficiency - The BSPDN concept, first proposed by imec in 2019, has shown potential in enhancing power-performance-area-cost (PPAC) advantages, particularly in high-density and high-drive logic applications [26][27]. - In a comparative study, the use of BSPDN in switch domain designs demonstrated a significant reduction in IR drop by 122mV and a 22% decrease in core area compared to traditional front-end power delivery networks [31]. Group 4: Future Directions - The roadmap for wafer-to-wafer hybrid bonding aims to achieve 200nm interconnect spacing, necessitating advancements in bonding processes and equipment to meet the precision required for high-density interconnects [14][15]. - The integration of nanoscale through-silicon vias (nTSV) is expected to facilitate seamless front-to-back connections, enhancing the overall architecture of CMOS 2.0 [21][24].