Core Viewpoint - The RISC-V instruction set architecture, characterized by its open-source nature, presents significant opportunities to break the traditional path dependence in the chip industry and establish a self-controlled computing foundation [1] Group 1: Industry Insights - Shenzhen has developed a leading industrial cluster in high-performance RISC-V microcontrollers (MCUs) [3] - Current integrated circuit industry support policies primarily focus on advanced logic processes of 28nm and below, which does not align with the RISC-V chips that mainly utilize mature processes of 55nm and 40nm in strategic fields such as automotive electronics and IoT [3] - The mismatch in policy direction restricts local enterprises from breaking into high-value markets, hindering Shenzhen's strategic advantage in the open-source chip ecosystem [3] Group 2: Policy Recommendations - It is suggested to establish a special fund within the municipal industrial funds to subsidize RISC-V chip projects that adopt mature processes like 55nm and 40nm for initial engineering tape-outs [4] - Reforming the subsidy policies for IP and EDA tools is recommended to support the core toolchain of the RISC-V ecosystem, with a focus on projects using domestic or open-source RISC-V IP [4] - In consumer electronics sectors where Shenzhen has advantages, it is proposed to facilitate connections between chip design companies and terminal manufacturers to promote application demonstration projects that prioritize local RISC-V chip solutions [4]

Core Insights - Guoxin Technology has successfully tested its newly developed neural network processor DPNPU (Dataflow Parallel NPU) internally, aimed at high-performance AI processing for edge and endpoint computing [1] - The DPNPU is designed to optimize complex and variable computing tasks in AI applications, focusing on achieving the best balance between power consumption, performance, and flexibility [1] Technical Specifications - The DPNPU supports a flexible computing power configuration ranging from 0.5 to 4.8 TOPS, allowing for linear scalability to provide customized AI computing solutions for various scenarios [2] - It utilizes an innovative open architecture compliant with the RISC-V instruction set architecture, featuring a dedicated Task Distribution & Synchronization (TDS) hardware scheduling engine for efficient task management and data flow control [2] - The DPNPU includes over 90 neural network operators, covering CNN and RNN architectures, and supports various RNN variants such as LSTM and GRU, with provisions for future AI model adaptations [2] - It supports post-training quantization (PTQ) techniques, offering symmetric, asymmetric, layer-wise, and channel-wise quantization methods, while maintaining model accuracy and significantly reducing computational resource and storage space requirements [2] Software Ecosystem - To lower the development threshold for AI applications, Guoxin Technology has built a complete software ecosystem around the DPNPU, named C*Core NPU Studio, which integrates a comprehensive suite of tools, drivers, and runtime software [3] - The C*Core NPU Studio provides end-to-end model deployment capabilities, including model conversion, preprocessing, quantization, compilation, and simulation tools [3] - The runtime support includes inference framework software and various extended soft operator libraries, while the driver is compatible with mainstream CPU platforms like RISC-V and supports different application environments such as Linux, RTOS, and Bare-metal [3] Market Positioning - The DPNPU architecture has been validated for feasibility, energy efficiency, and software stack, laying a foundation for the continued development of NPU technology and the growth of edge and endpoint AI chip applications [3] - Compared to cloud AI, edge and endpoint AI offer significant advantages such as real-time response, data privacy protection, and low network dependency, which demand higher energy efficiency and computing density from chips [3]