RTL

Search documents
AMD Vitis™ HLS Overview
AMD· 2025-08-10 04:54
HLS Design Flow in Vitis Unified IDE - The AMD Vitis Unified IDE supports a bottom-up approach for heterogeneous system design, enabling the creation of individual system elements as components [2] - The IDE offers various development flows, including HLS, AI Engine Graph, Embedded, and System Development, along with tools for report analysis and user-managed workflows [2] - The Vitis Components view provides hierarchical project navigation, organizing source files and test benches [14] HLS Component Creation and Configuration - An HLS component can be created using the 'Create HLS Component' wizard, which guides users through the process [3] - The HLS component configuration file stores commands and settings for synthesis, simulation, and export [6] - Users can specify the top-level function to be synthesized, with underlying functions also synthesized into RTL [9] - The tool automatically applies uncertainty margin during synthesis to create RTL that is more likely to meet timing in Vivado [11] - The flow target can be set to either 'Vivado IP' or 'Vitis kernel', with the default 'Vivado IP' setting generating a .zip file [11][12] Verification and Packaging - C simulation can be run with default settings, generating a summary report and simulation log file [16][17] - RTL cosimulation verifies the generated RTL against the C test bench to ensure identical results [20] - The design can be packaged into a reusable IP component, with options for Vivado IP, Vitis kernel (.xo file), or RTL output [22][23][24][25] RTL Analysis and Implementation - HLS provides estimations for resource utilization and timing, but accurate RTL analysis requires running Vivado RTL synthesis and place-and-route [25][26] - Vivado synthesis and implementation can be configured before execution using the Implementation settings [26]
RTL for Programable NoC (Modular NoC) Part 2 – Adding XPMs
AMD· 2025-07-17 16:00
Welcome to part two of the Modular NoCs series. In this video, you are going to learn about how to add XPMs into your design to utilize the modular NoC. To refresh your memory, the modular NoC solution is comprised of three main steps.Step one is to connect all AXI busses that want to utilize the NoC to Xilinx parameterizable macros or XPMs. . The second step of the process is to add constraint files (or XDCs) to the design that define connectivity and quality of service parameters for each individual NoC c ...
RTL for Programable NoC (Modular NoC) Part 4 – validate_noc Command
AMD· 2025-07-17 16:00
Welcome to part four of the modular NoC series. In this video, you're going to learn about the validate_noc command. At this stage, we know how to connect all AXI busses by utilizing XPMs and how to define multiple constraints like connectivity addressing QoS and bandwidth by using constraint files (or XDCs).The final step in this three step process is to run the validate_noc command. This video focuses on this command. The validate_noc command validates the NoC topology for the entire system. The validate_ ...
RTL for Programable NoC (Modular NoC) Part 3 – Creating Connections & Adding Properties
AMD· 2025-07-17 16:00
Modular NoC Solution Overview - The modular NoC solution involves connecting AXI busses to Xilinx parameterizable macros (XPMs), adding constraint files (XDCs) to define connectivity and quality of service (QoS) parameters, and running the validate NoC command [2] - The focus is on adding constraint files (XDCs) to define connectivity and QoS parameters for each NoC connection [3] XDC Constraint File Configuration - XDC files can be specified per module and do not require RTL elaboration when modified [4] - The XDC file defines the addressing aperture of the NSU, ensuring addresses are routed appropriately; if the NSU is in the block design, the aperture is defined in the BD and doesn't need specification in the XDC [6] - The XDC file creates NoC connections between NMUs and NSUs and applies QoS constraints to those connections [7] - Setting the USED_IN property of the XDC file to "synthesis_pre" is necessary for the validation command to find the NoC constraints [10] Creating NoC Connections - The "get_noc_interfaces" command is used to get a list of available NoC interfaces in the design [11] - The "create_noc_connection" command is used to create connections between NMUs and NSUs [12][15] - The "set_property" command is used to specify QoS properties like READ_BANDWIDTH, READ_AVERAGE_BURST, WRITE_BANDWIDTH, and WRITE_AVERAGE_BURST, as well as TDEST_IDs for the connections [15][16]