Hello and welcome. This video will be guiding you through an overview of the AMD Versal NoC-based hard DDR memory controllers. It will explore the architecture, configuration, simulation methodology, and hardware validation approaches for integrating and using DDR memory through the programmable Versal network on chip, or NoC.This is targeted toward engineers and system architects looking to optimize memory access on Versal devices. Let's get started. We’ll begin with an introduction to the AMD Versal™ prog ...

Welcome to part two of the Modular NoCs series. In this video, you are going to learn about how to add XPMs into your design to utilize the modular NoC. To refresh your memory, the modular NoC solution is comprised of three main steps.Step one is to connect all AXI busses that want to utilize the NoC to Xilinx parameterizable macros or XPMs. . The second step of the process is to add constraint files (or XDCs) to the design that define connectivity and quality of service parameters for each individual NoC c ...