Core Viewpoint - The recent adjustment of shareholding ratios by major players in the domestic semiconductor packaging and testing industry, namely Changdian Technology, Tongfu Microelectronics, and Huada Semiconductor, aims to optimize the equity structure of Huajin Semiconductor, enhancing its technological research and development capabilities and driving high-quality industry growth [1][13]. Shareholding Changes - The shareholding ratio of Changdian Technology, Tongfu Microelectronics, and Huada Semiconductor in Huajin Semiconductor has been reduced from approximately 4.325% to 2.747% [1]. - Other notable shareholders include Beijing Zhongke Micro Investment Management Co., Ltd. and Wuxi Guochuang Chip Investment Management Partnership, which also experienced changes in their shareholding percentages [4][14]. Company Background - Huajin Semiconductor was established in 2012 as a collaborative effort among leading packaging and testing companies and research institutions, with a registered capital of 462.4682 million yuan [14]. - The company focuses on advanced packaging technologies such as TSV, 2.5D/3D, and Chiplet, and plays a crucial role in key technology breakthroughs and standard formulation within the industry [14][16]. Technological Capabilities - Huajin Semiconductor has built a leading semiconductor packaging and testing research center in China, with a team of nearly 100 researchers, over half of whom hold doctoral or master's degrees [16]. - The company has applied for over 1,300 patents, ranking among the top globally in the number of patents related to 2.5D/3D packaging and TSV technologies [16].

Core Viewpoint - The demand for ultra-thin wafers is increasing due to the transition from planar SoC to 3D-IC and advanced packaging, which enhances performance and reduces power consumption [1][18]. Group 1: Thin Wafer Processing - The total thickness of HBM modules, which include 12 DRAM chips and basic logic chips, is still less than that of high-quality silicon wafers [1]. - Thin wafers play a crucial role in fan-out wafer-level packaging and advanced 2.5D and 3D packaging for AI applications, which are growing faster than mainstream ICs [1]. - The processing of ultra-thin wafers requires careful decisions regarding temporary bonding adhesives, carrier wafers, and debonding processes [1][3]. Group 2: Challenges in Wafer Thinning - Engineers face challenges in preventing defects or micro-cracks, especially at the wafer edges, which can significantly impact yield [10]. - The thinning process involves a balance of grinding, chemical mechanical polishing (CMP), and etching to meet strict total thickness variation (TTV) specifications [8]. - The most common TSV architecture in silicon features a diameter of 11 micrometers and a depth of 110 micrometers, with a barrier metal and oxide insulation layer occupying 1 micrometer of that diameter [9]. Group 3: Temporary Bonding and Debonding - The industry is refining thinning steps, adhesives, and debonding chemicals, with temporary bonding typically performed under vacuum thermal compression or UV exposure [3][7]. - Glass and silicon carrier wafers are both used, with glass being popular due to its thermal expansion coefficient (CTE) compatibility with silicon [5]. - Mechanical debonding methods are preferred for thinner wafers, as they allow for lower stress levels and better thermal budgets [15]. Group 4: Adhesive Properties and Requirements - Ideal adhesives should bond at low temperatures and withstand high-temperature processing without degrading performance [7]. - The adhesive's uniformity in thickness is critical, as any inconsistency can lead to uneven back grinding and processing challenges [7][8]. - The choice of adhesive is influenced by temperature stability, with some materials capable of withstanding temperatures up to 350°C [7]. Group 5: Yield and Reliability - Chip manufacturers are seeking customized solutions for specific device types, emphasizing the need for tool reliability and process repeatability [2]. - The industry is focused on achieving high yield and reliability in producing ultra-thin devices with thicknesses below 50 micrometers [18]. - The management of back and edge defects is essential for maintaining yield, with selective plasma etching and CVD being employed to mitigate edge defects [10][11].