Core Viewpoint - DNP has successfully developed a 10nm NIL nanoimprint lithography mask, aimed at meeting the miniaturization demands of advanced logic chips for applications such as smartphones and data centers, with plans for mass production by 2027 [1][3]. Group 1: Product Development - The newly developed 10nm NIL nanoimprint lithography mask can be used for circuit patterning equivalent to 1.4nm logic semiconductors [1]. - DNP aims to increase sales from its nanoimprint-related business to 4 billion yen by the fiscal year 2030 [1]. Group 2: Market Demand and Technology - There is a growing demand for advanced process logic semiconductors due to the continuous improvement in terminal device performance, driving the evolution of production technologies based on extreme ultraviolet (EUV) lithography [3]. - DNP's nanoimprint lithography technology offers a new path to reduce exposure energy consumption and optimize cost structures, addressing concerns over high capital expenditure and environmental impact associated with EUV [3][4]. Group 3: Technical Innovations - DNP has introduced self-aligned double patterning (SADP) technology to double the graphic density, achieving the 10nm line width for the nanoimprint lithography mask [4]. - The energy consumption during the exposure phase can be reduced to about one-tenth of that of current mainstream processes, according to company estimates [4]. Group 4: Industrialization and Future Plans - DNP has initiated customer evaluations and is in communication with semiconductor manufacturers to prepare for mass production starting in 2027 [4]. - The company plans to showcase the 10nm NIL nanoimprint lithography mask at SEMICON Japan 2025, aiming to enhance communication with global semiconductor manufacturers and equipment suppliers [5].