Core Viewpoint - ECARX has unveiled its first 32-bit RISC-V ISA-based processor design, EXP01, which features a dual-core safety architecture that has achieved the highest level of functional safety certification ISO 26262 ASIL-D, enhancing reliability for critical automotive functions [2][3] Group 1: Product Announcement - ECARX introduced the EXP01 processor at the 2025 European RISC-V Summit, marking a significant technological breakthrough for the company [1] - The EXP01 processor is designed with a dual-core safety architecture that continuously verifies the operation of both cores, ensuring high reliability for advanced driver assistance and smart cockpit interfaces [2] Group 2: Future Development Plans - ECARX outlined its roadmap for the next generation of automotive-grade microcontrollers (MCUs), which will be scalable and designed for smart cockpit and body domain control applications, compliant with ISO 26262 ASIL-B safety standards [2] - The upcoming MCUs will support current and future encryption protocols, ensuring compliance with international data regulations [2] Group 3: Strategic Collaborations - During the event, ECARX's R&D director engaged in technical discussions with leading RISC-V developers, including StarFive Technology, laying the groundwork for joint R&D initiatives aimed at accelerating the integration of RISC-V-based computing platforms with next-generation automotive architectures [2] Group 4: Company Vision - The CEO of ECARX emphasized that the launch of EXP01 is a critical step towards providing a high-reliability open architecture computing platform for the automotive industry, aiming to enhance performance and safety through a global partner ecosystem [3] - The open architecture of RISC-V is seen as a means to accelerate innovation and optimize costs, aligning with the company's goal to help automotive manufacturers lead technological advancements [3]