Core Viewpoint - The article discusses the open call for next-generation 10nm and 7nm design projects based on Fully Depleted Silicon-On-Insulator (FD-SOI) technology, highlighting its potential to enhance the competitiveness of European semiconductor companies [1][3]. Group 1: Technology and Development - The FD-SOI technology is recognized for its ultra-low power capabilities applicable in digital, analog, and RF designs, with a transition planned from 22nm to 10nm and then to 7nm over the next two years [1]. - The FAMES FD-SOI pilot line will feature 110 pieces of equipment across four sites, including 90 pieces dedicated to 300mm wafer production, with a key immersion lithography tool set to operate from December 2023 [3][4]. - The pilot line aims to provide exploratory Process Design Kits (PDKs) for performance evaluation and multi-project wafer testing, focusing on embedded non-volatile memory technologies [5][6]. Group 2: Industry Collaboration and Impact - Participants in the initiative come from 18 countries, emphasizing a balance between industry and academia, which is crucial for fostering innovation [2]. - The project is seen as a strategic structure to support the entire EU semiconductor value chain, promoting collaboration among industry players, SMEs, startups, and research institutions [7][9]. - Major industry players like Nokia and Stellantis are involved, indicating the initiative's significance for the development of European chips and applications [8][9]. Group 3: Future Prospects - Test chips using the 10nm FD-SOI process are expected to be available by 2027, with ongoing development of specific process steps and modules [3][7]. - The focus on advanced memory technologies, such as MRAM, aims to address security applications and ultra-low power AI memory computing [6].