Core Viewpoint - The article focuses on the latest advancements in semiconductor technology presented at the VLSI conference, highlighting innovations in chip manufacturing, including digital twins, advanced logic transistors, and future interconnects, as well as comparisons between Intel's 18A process and TSMC's technologies [1]. Group 1: FlipFET Design - Despite various restrictions, China continues to advance in semiconductor R&D, with Peking University's FlipFET design gaining significant attention for its novel patterning scheme that achieves PPA similar to CFET without the challenges of monolithic or sequential integration [2]. - The FlipFET technology involves a process where NMOS is formed on the front side and PMOS on the back side of the wafer, showcasing good performance for both types of transistors [8][10]. - The main drawback of FlipFET is its cost, as it requires multiple back-end processes and is more susceptible to wafer warping and alignment errors, potentially affecting yield [12]. Group 2: DRAM Developments - DRAM is at a pivotal point in its five-year roadmap with two key advancements: 4F2 and 3D technologies, with 4F2 expected to increase density by 30% compared to 6F2 without reducing minimum feature size [16][23]. - The 4F2 architecture necessitates vertical channel transistors to fit within the unit size, presenting manufacturing challenges due to high aspect ratios [24][31]. - 3D DRAM is being developed concurrently, with Chinese manufacturers showing strong motivation to innovate in this area due to its independence from advanced lithography technologies [36]. Group 3: Digital Twin Technology - Digital twin technology is becoming essential in semiconductor design and manufacturing, allowing for design exploration and optimization in a virtual environment before physical production [79]. - This technology spans atomic-level simulations to wafer-level optimizations, enhancing productivity and yield in semiconductor fabrication [80][87]. - The implementation of "unmanned" fabs is a future goal, aiming for automated maintenance and operation without human intervention, which poses challenges in standardizing processes across different equipment vendors [92]. Group 4: Intel's 18A Process - Intel's 18A process, set to enter mass production in late 2025, combines Gate-All-Around transistors with a PowerVia back power network, significantly reducing interconnect spacing and improving yield [74][78]. - The 18A process claims a 30% reduction in SRAM size compared to Intel's 3rd generation baseline, with performance improvements of approximately 15% at the same power consumption [76]. - The process also features a reduction in the number of front metal layers and an increase in back metal layers to support the new architecture, indicating a shift towards more efficient manufacturing [77].