Core Insights - The fifth RISC-V China Summit will be held from July 16 to 19, 2025, in Shanghai, featuring a main forum, nine vertical sub-forums, five workshops, and a 4,500 square meter technology exhibition area, attracting hundreds of companies, research institutions, and open-source technology communities [1] - The presentation by the market director of Hanjian Software highlighted the challenges and innovations in verifying high-performance RISC-V multi-core processors, laying a solid foundation for the proliferation and development of RISC-V processors [3] Development Stages of Xiangshan Processors - The Xiangshan processor series has undergone three significant development phases: - Yanqi Lake (First Generation): Focused on architecture exploration and foundational technology, successfully implementing out-of-order execution architecture [3] - Nanhu (Second Generation): Achieved a performance leap, benchmarking against ARM Cortex-A76, recognized as a high-performance RISC-V processor core [3] - Kunming Lake (Third Generation): Targets data centers and high-performance computing, benchmarking against ARM Neoverse N2, supporting 64-core large-scale high-performance SoC system architecture [3] Key Technologies in Kunming Lake - Multi-core scalability: Architecture supports expansion from 64 to 256 cores to meet future technological demands [4] - High-speed interconnect bus: Utilizes new high-bandwidth, low-latency NoC technology for efficient data exchange [4] - Strong consistency memory system: Introduces large-scale multi-level cache and directory-based cache coherence protocols to ensure system stability [4] Challenges in Multi-core CPU Verification - The verification process faces three key challenges: - Large scale: Multi-core systems involve complex buses, multi-level caches, and peripheral interfaces, requiring FPGA resources far exceeding traditional platforms [4] - High performance requirements: Aiming for a target operating speed of 10 MHz on FPGA to support OS operation and hardware-software co-verification [4] - Debugging difficulties: Ensuring cache coherence, bus integrity, and scheduling optimization poses significant debugging challenges, with deep-rooted bugs in cross-core interactions being hard to locate [4] Verification Methodology - A systematic four-step verification methodology was proposed: - Design porting and adaptation: Automating the adaptation from ASIC to FPGA, including clock tree, storage model, and interface IP conversion [5] - Compilation and resource optimization: Balancing resource usage and efficient compilation in large-scale designs [6] - Progressive bring-up strategy: Gradually expanding from single-core to multi-core systems to reduce debugging complexity [6] - Hardware-software co-debugging technology: Utilizing hardware emulation and backdoor loading techniques for rapid fault localization and kernel loading speed breakthroughs [6] Future Directions - The Xiangshan team aims to deepen verification efficiency, explore larger-scale device cascading, and encourage EDA vendors to develop more features supporting multi-core system verification, such as low-power verification and dynamic power analysis [6][7] - The development of Xiangshan processors signifies significant progress in China's high-performance RISC-V processor field, providing replicable and scalable standardized verification methods for the industry [7]

第五届RISC-V中国峰会于2025年7月16至19日在上海张江科学会堂隆重举办，本届峰会设置1场主论 坛、9场垂直领域分论坛、5场研习会、11项同期活动，以及4,500平方米未来科技展览区，汇聚数百家 企业、研究机构及开源技术社区参会。 在7月18日的EDA分论坛上，中国科学院计算技术研究所特别研究助理，北京开源芯片9研究院特别研 究助理徐易难带来了主题为"SVM：可用综合方法实现RISC-V处理器的高效验证"的演讲。 随着芯片设计日益复杂，处理器验证成为了芯片开发中的瓶颈问题。徐易难详细阐述了处理器验证的现 状、挑战和创新方法，提出SVM作为一种高效的硬件验证方法，能够大幅提升RISC-V处理器验证的效 率。 REF电路代码实现：现有的参考模型（REF）通常以软件模拟器的形式存在，设计简单且可靠，但缺乏 高效的硬件实现方式。如何将现有的软件REF高效地迁移到硬件中，是SVM面临的首要问题。 硬件REF执行效率：由于DUT设计复杂且微结构丰富，而REF则需要设计得简单以保证功能可靠，因此 如何提升硬件REF的执行效率，成为SVM的一大挑战。 调试和可追溯性问题：硬件环境缺乏对传统软件调试工具的支持（如断言、 ...