Core Viewpoint - The article discusses a significant architectural shift from speculative execution to a deterministic, time-based execution model in modern CPUs, which aims to enhance efficiency and reliability while addressing the challenges posed by speculative execution, such as energy waste and security vulnerabilities [2][3][19]. Group 1: Architectural Shift - Speculative execution has been a dominant paradigm in CPU design for over three decades, allowing processors to predict branch instructions and memory loads to avoid stalls [2]. - The transition to a deterministic execution model is based on David Patterson's principle of simplicity, which enhances speed through a simpler design [3]. - Recent patents have introduced a new instruction execution model that replaces speculation with a time-based, fault-tolerant mechanism, ensuring a predictable execution flow [3][4]. Group 2: Deterministic Execution Model - A simple timer is utilized to set the exact execution time for instructions, which are queued based on data dependencies and resource availability [4]. - This deterministic approach is seen as a major architectural challenge since the advent of speculative architectures, particularly in matrix computation [4][5]. - The new model is designed to support a wide range of AI and high-performance computing workloads, demonstrating scalability comparable to Google's TPU while maintaining lower costs and power consumption [4][5]. Group 3: Efficiency and Performance - The deterministic scheduling applied to vector and matrix engines allows for a more efficient execution process, avoiding the pitfalls of speculative execution [5][6]. - Critics argue that static scheduling may introduce delays, but the article contends that traditional CPUs already experience delays due to data dependencies and memory reads [6][7]. - The time counter method identifies delays and fills them with useful work, thus avoiding rollbacks and enhancing energy efficiency [6][19]. Group 4: Programming Model and Compatibility - From a programmer's perspective, the execution model remains familiar, as RISC-V code compilation and execution processes are unchanged [14][16]. - The key difference lies in the execution contract, which guarantees predictable scheduling and completion times, eliminating the unpredictability associated with speculative execution [14][15]. - The deterministic model simplifies hardware, reduces power consumption, and avoids pipeline flushes, particularly benefiting vector and matrix operations [15][16]. Group 5: Applications in AI and Machine Learning - In AI and machine learning workloads, vector loads and matrix operations dominate runtime, and the deterministic design ensures high utilization and stable throughput [18][19]. - The deterministic model is compatible with existing RISC-V specifications and mainstream toolchains, allowing for seamless integration into current programming practices [18][19]. - The industry is at a turning point, as the demand for AI workloads increases, highlighting the limitations of traditional CPUs reliant on speculative execution [19].