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美对华EDA出口限制,挑战与机遇并存
Investment Rating - The report does not explicitly state an investment rating for the industry or specific companies involved in EDA [1]. Core Insights - The new U.S. export restrictions on EDA software and technology to China are more comprehensive than previous regulations, affecting a broader range of integrated circuit levels without specific nanonode restrictions [2][7]. - Cadence and Synopsys reported revenues of $570 million and $990 million from China in fiscal year 2024, representing 12% and 16% of their total revenues respectively, indicating a significant market share in China [2][7]. - The restrictions are expected to lead to a short-term revenue decline for Cadence and Synopsys in China, but long-term impacts may be mitigated by growth in other regions [2][7]. - The restrictions may accelerate the localization of EDA tools in China, as seen with Huawei's progress in developing domestic EDA alternatives [3][8]. Summary by Sections Export Restrictions - On May 29, 2025, Cadence and Synopsys received notification from the U.S. Department of Commerce regarding new export restrictions that require licenses for EDA software and technology exports to China, particularly involving military end users [2][6]. - The new policy is broader than previous restrictions, which were limited to advanced nanonodes, now encompassing all integrated circuit levels from wafers to packaging [2][7]. Market Impact - Cadence and Synopsys, along with Siemens EDA, hold over 70% of the EDA market share in China, indicating their significant presence [2][7]. - Synopsys has already suspended services and sales in China and is assessing the impact of the new restrictions on its business [2][7]. Localization Opportunities - The export restrictions are seen as a catalyst for accelerating the domestic development of EDA tools in China, with Huawei achieving significant milestones in EDA software development [3][8]. - The localization efforts have progressed to the point where Huawei has independently mass-produced a 7nm chip, indicating advancements in EDA capabilities [3][8].