Core Viewpoint - SK Hynix has showcased its latest 5-bit single-cell NAND flash technology at the 2025 IEDM conference, which improves speed and durability by splitting 3D NAND cells and reducing the required voltage states by about two-thirds [1]. Group 1: Technology Overview - The new 4D 2.0 technology allows for bypassing voltage state barriers, avoiding the simple increase of bits beyond 4-level (QLC) in NAND cells [1]. - NAND cells store charge and read it by measuring the threshold voltage of the cell, with the number of voltage states doubling with each additional bit [1]. - The 5-bit PLC (Penta-Level Cell) technology can achieve 32 states with 31 threshold voltages, which is an advancement over existing technologies [2]. Group 2: Commercial Viability - Currently, QLC 3D NAND flash is commercially produced, while PLC flash has not yet reached commercial production due to low read reliability and durability [3]. - PLC technology is attractive as it can increase NAND chip capacity by 25% compared to QLC technology without necessarily increasing the number of stacking layers [3]. - SK Hynix aims to effectively split NAND cells into two independent parts, each with fewer voltage states, to enhance performance [3]. Group 3: Manufacturing Process - Achieving the PLC technology requires additional semiconductor processing steps, such as splitting elliptical cells and adding connections to each half [6]. - Each half-cell has six voltage states, leading to a total of 36 states, which meets the requirements for PLC flash [6]. - The simultaneous reading of both half-cells allows for a 20-fold increase in reading speed compared to non-MSC PLC flash [7]. Group 4: Future Prospects - If an MSC half-cell can achieve eight voltage states, the entire cell would have 64 states, sufficient for a 6-bit HLC (Hexa-Level Cell) requirement, potentially offering higher capacity than QLC chips [8].