Core Viewpoint - A French team has developed the first hybrid memory technology that supports adaptive local training and inference for artificial neural networks, addressing a long-standing technical bottleneck in edge AI efficiency [1][2]. Group 1: Research and Development - The research, led by CEA-Leti, demonstrates that on-chip training is feasible and can achieve competitive accuracy, eliminating the need for off-chip updates and complex external systems [2]. - The innovative technology enables edge systems and devices, such as autonomous vehicles and medical sensors, to learn from real-time data and adapt models on the fly while controlling energy consumption and hardware wear [2]. Group 2: Technical Challenges - Edge AI requires both inference (reading data to make decisions) and learning (updating models based on new data), but existing storage technologies excel at only one of these tasks [2][3]. - Memristors are efficient for inference due to their ability to store analog weights, while ferroelectric capacitors (FeCAPs) allow for quick, low-energy updates but are unsuitable for inference due to their destructive read operations [2]. Group 3: Hybrid Approach - The team proposes a hybrid method where forward and backward passes use low-precision analog weights stored in memristors, while updates are performed using higher precision FeCAPs [5]. - Memristors are periodically reprogrammed based on the most significant bits stored in FeCAPs to ensure efficient and accurate learning [5]. Group 4: Unified Memory Stack - A unified memory stack composed of silicon-doped hafnium oxide and a titanium scavenging layer has been designed, allowing the dual-mode device to operate as both FeCAPs and memristors [7]. - The same storage unit can be utilized for precise digital weight storage (training) and analog weight representation (inference) based on its state [7]. Group 5: Implementation and Testing - A digital-to-analog transfer method enables the conversion of hidden weights in FeCAPs to conductance levels in memristors without the need for formal digital-to-analog converters [8]. - The hardware was manufactured and tested using standard 130-nanometer CMOS technology, integrating both types of memory and their peripheral circuits into a single chip [8].