Core Viewpoint - Kioxia Holdings (Kioxia HD) is focusing on advancing its flagship product BiCS FLASH technology to meet the growing demands of artificial intelligence (AI) by enhancing bit density, reliability, performance, and energy efficiency [1][6]. Summary by Sections Memory Technology Evolution - Kioxia HD's memory capacity has increased from 4M bits in 1991 to 2T bits in the eighth generation of BiCS FLASH, representing a 500,000-fold increase [1]. - The company emphasizes that the cost competitiveness of NAND flash memory depends on the number of bits that can be loaded onto a chip, with various methods to increase bit density including layer stacking and architectural innovations [1][3]. Bit Density Maximization - Kioxia HD combines layer stacking with planar area reduction to maximize bit density, utilizing new architectures like CBA (CMOS Direct Bonding Array) and early adoption of QLC technology [3][4]. - The OPS (On Pitch SGD) technology has been developed in collaboration with partners to reduce area overhead in the word line layer, enhancing the efficiency of memory designs [3]. New Architectures and Technologies - The introduction of CBA technology in the eighth generation reduces wiring overhead between CMOS and memory cells, allowing for better performance under optimal conditions [4]. - Kioxia HD has been producing QLC products since the fourth generation of BiCS FLASH, balancing performance and reliability to lower costs [6]. Future Technology Strategy - The company plans to develop high-capacity and high-performance products by combining layer stacking and planar reduction, targeting enterprise and data center SSD markets [7]. - Kioxia HD aims to leverage CBA technology to create competitive products that meet advanced application demands while maintaining investment efficiency [9]. Market Expansion Efforts - Kioxia HD is exploring new markets beyond TLC and QLC NAND, including the development of OCTRAM for low-power AI applications and X-FLASH to bridge the latency gap between TLC NAND and DRAM [11]. - The CXL-XL memory, which allows memory sharing between CPUs, is set to address the growing need for large-capacity, low-latency memory solutions [13].