Core Viewpoint - TSMC has launched a new advanced packaging platform called CoPoS (Chip-on-Panel-on-Substrate), which integrates the advantages of CoWoS and FOPLP, addressing warping and cost issues for large AI chips, positioning it as a key technology for next-generation efficient packaging [2][4]. Group 1: CoPoS Technology Overview - CoPoS technology utilizes a square panel design and replaces traditional circular silicon interposer with materials like glass or sapphire, significantly improving area utilization and yield for large AI and HPC chip applications [2][4]. - The panel sizes for CoPoS include 310×310mm, 515×510mm, and 750×620mm, targeting large-scale AI and HPC chip applications [4][5]. - TSMC plans to establish the first CoPoS experimental line in 2026 and aims for mass production by the end of 2028, with additional facilities in Arizona, USA [2][5]. Group 2: Comparison with CoWoP - CoWoP (Chip on Wafer on PCB) differs from CoPoS in that it uses a PCB instead of a glass substrate, focusing on high-end chip cooling and performance enhancement, while CoPoS emphasizes packaging efficiency and scalability [5]. - CoPoS is expected to significantly increase advanced packaging capacity for high-end AI chips, while CoWoP is more specialized for high-performance GPU chips [5].