Core Insights - Transition Metal Dichalcogenides (TMDs) like WSe₂ and MoS₂ are considered potential alternatives to silicon in advanced GAA transistors due to their two-dimensional nature, which minimizes interface scattering and maintains carrier mobility [1] - However, TMDs face significant challenges, including weak adhesion between layers and high energy barriers at contact points, necessitating major improvements in traditional CMOS processes for successful integration [1] Material Preparation Challenges - The technology for growing TMDs on substrates like sapphire is mature, but transferring these films to silicon wafers for further processing is difficult to scale [3] - Direct growth on the final substrate is preferred by commercial fabs to avoid complexities and contamination risks associated with film transfer [3] - High-temperature chemical vapor deposition (CVD) required for TMDs can damage underlying dielectric layers, and thermal expansion mismatches can weaken adhesion [3] - Researchers are exploring various solutions, including a thin passivation oxide layer to protect TMDs during processing and a selective growth technique to reduce growth time and temperature [3] Integration Approaches - CEA-Leti and Intel have developed a "post-channel processing" integration scheme that retains most of the silicon-based GAA transistor process flow, using a Si/SiGe multilayer stack [4] - This method involves replacing the metal gate and self-aligned contact etching while filling the channel with ALD MoS₂ or WSe₂ [4] Contact Formation - The interface between the semiconductor channel and contact metals is critical for device performance, with surface damage and contamination posing significant risks [6] - Techniques such as depositing aluminum oxide and HfO₂ layers after TMD deposition can protect the channel and improve adhesion [6] - TSMC's research indicates that the contact characteristics of PMOS TMD devices show a significant gap from actual performance, with alternative doping providing a more robust solution [6][7] Complementary Logic and Heterogeneous CFET - Direct growth of n-type and p-type channel materials for complementary logic remains a challenge, with WSe₂ and MoS₂ being the leading candidates [9] - Research teams are exploring layer transfer methods for heterogeneous vertical CFET structures, achieving better performance metrics compared to pure silicon CFETs [9] - Purdue University is addressing parasitic capacitance in source-drain overlap regions by utilizing CVD-grown graphene and MoS₂ for contact regions [9] Mechanical and Thermal Properties - As researchers begin to fabricate device-like structures, evaluating their mechanical and thermal properties becomes essential [11] - TMDs exhibit high strength as bulk materials, but additional support may be needed at monolayer thickness [11] - Thermal conductivity is a concern, with TMDs and HfO₂ showing poor out-of-plane thermal conductivity, necessitating efficient heat dissipation through metal contacts [11] Future Outlook - TMDs have evolved from research subjects to serious contenders as silicon alternatives, but fundamental issues must be resolved before mass production [12] - CFETs based on silicon also face significant challenges, but TMDs introduce new materials and processes with many unknowns [12]