Core Insights - The PCI Express (PCIe) 8.0 specification aims to achieve a data rate of 256.0 GT/s, with a maximum bidirectional throughput of 1 TB/s through x16 configuration, set to be released to members in 2028 [2][4] - PCIe 8.0 is expected to support emerging applications such as artificial intelligence/machine learning, high-speed networking, edge computing, and quantum computing, as well as data-intensive markets like automotive, hyperscale data centers, high-performance computing (HPC), and military/aerospace [2][4] - The UCIe 3.0 specification has been announced, enhancing performance with support for data rates of 48 GT/s and 64 GT/s, marking the next phase in the evolution of open chip standards [5][9] PCIe 8.0 Specification Features - PCIe 8.0 will double the data rate to 256 GT/s, continuing the tradition of doubling bandwidth every three years to support next-generation applications [4] - The demand for PCIe technology is expected to grow due to its high bandwidth, scalability, and energy efficiency, particularly in data-intensive applications [4][5] UCIe 3.0 Specification Highlights - UCIe 3.0 introduces runtime recalibration for improved power efficiency and expanded sideband coverage for more flexible multi-chip configurations [5][6] - The specification supports a raw bit rate of 256.0 GT/s and up to 1 TB/s bidirectional throughput through x16 configuration [5][9] - UCIe 3.0 emphasizes higher scalability, flexibility, and interoperability, driving innovation in the chiplet ecosystem [6][9]