Summary of Semiconductor Advanced Packaging Industry Conference Call Industry Overview - The advanced packaging industry has become a key path to surpass Moore's Law, addressing physical bottlenecks such as high leakage power, exponential cost increases, and signal transmission losses in processes below 7nm [1][2][3] Core Technologies and Their Applications - **CoWoS-S**: Utilizes silicon interposer and TSV for high-performance interconnection, primarily used in flagship AI chips like NVIDIA H100/A100 and AMD MI300, but at a high cost [1][6] - **CoWoS-L**: Balances performance and cost through local interconnects, currently accounting for about 60% of TSMC's 2.5D packaging for Intel, and is the direction for future large AI chips and domestic companies like Huawei and Cambricon [1][6] - **CoPoS**: Replaces circular silicon interposer with rectangular panels, potentially increasing material utilization from 70%-75% to 100%. TSMC plans to trial production in 2026 and mass production in 2027, while domestic firms are in the research and prototyping phase [1][7] - **CoWoP**: Aims to eliminate the expensive substrate step by directly mounting chips onto PCBs, but is still in conceptual research due to engineering constraints [1][7] Industry Dynamics and Constraints - The necessity for advanced packaging arises from three main constraints: 1. **Physical Limits**: Quantum tunneling effects lead to significant leakage power increases as processes advance below 7nm and 5nm, making further miniaturization less cost-effective [2][3] 2. **Cost Constraints**: Increased complexity in processes raises overall costs exponentially due to more equipment, materials, and mask layers [2][3] 3. **Performance Bottlenecks**: Longer data and current transmission paths within chips lead to higher losses, hindering effective computational power release [2][3] Global and Domestic Players - Major global players in advanced packaging include TSMC, Intel, and Samsung, with OSAT firms like ASE also advancing their capabilities. Domestic firms like Changdian Technology are also positioning themselves in this space [4] Differences Between 2.5D and 3D Packaging - **2.5D Packaging**: Focuses on horizontal integration with multiple chips placed side by side on a silicon interposer, exemplified by CoWoS [5] - **3D Packaging**: Involves vertical stacking of chips, allowing for higher interconnection density and bandwidth, typically seen in HBM stacks [5] CoWoS Variants and Their Characteristics - **CoWoS-S**: High performance but high cost, used in flagship AI chips [6] - **CoWoS-R**: Uses organic RDL for flexibility and lower costs, suitable for cost-sensitive applications [6] - **CoWoS-L**: Aims for a balance between performance, cost, and size, suitable for future large AI chips [6] Future Trends and Directions - The penetration of CoWoS-L is expected to increase as domestic AI chip manufacturers like Huawei and Cambricon transition from CoWoS-S to CoWoS-L as their production volumes rise [6]