Core Viewpoint - The semiconductor industry is transitioning from a focus on transistor scaling to a more modular approach that emphasizes advanced packaging technologies, interconnect standards, and memory disaggregation to enhance performance without solely relying on shrinking transistor sizes [46][47]. Group 1: Transition to Advanced Packaging - High-performance computing is moving away from the "monolithic" era, with a shift towards decoupling functional modules and integrating them through advanced interconnect technologies [2]. - The transition from organic substrates to glass substrates marks a significant change in semiconductor packaging, with companies like Intel and SKC investing in this technology to reduce warpage and support larger package sizes [4][5]. - The glass substrate market is projected to reach $460 million by 2030 under optimistic adoption scenarios [5]. Group 2: Key Technologies Driving Change - Three key technologies are facilitating this transformation: glass substrates, Universal Chiplet Interconnect Express (UCIe), and Compute Express Link (CXL) [3]. - UCIe provides a standardized die-to-die interconnect technology that allows chiplets from different nodes and suppliers to work together within the same package [15]. - CXL enables memory pooling and disaggregation, addressing the "memory wall" issue by allowing processors to access shared memory resources dynamically [27][32]. Group 3: Glass Substrate Advantages - Glass substrates offer superior mechanical and thermal properties, effectively addressing warpage issues associated with organic substrates, especially in high-power applications [6][9]. - The transition to glass substrates allows for higher interconnect density and better signal integrity, which is crucial for advanced packaging designs [10][12]. - Glass substrates can support larger package sizes exceeding 100 mm × 100 mm, facilitating the integration of multiple chiplets [9][40]. Group 4: UCIe Development and Adoption - UCIe has evolved from initial versions focusing on 2D and 2.5D packaging to supporting 3D integration, enhancing signal density and interoperability among chiplets [18][20]. - The latest UCIe 3.0 version, set to release in August 2025, will support data rates of up to 64 GT/s, doubling the bandwidth capabilities of earlier versions [16]. - NVIDIA's adoption of UCIe for integrating custom IP modules into its GPUs highlights the growing industry recognition of this standard [25]. Group 5: CXL's Role in Memory Management - CXL has evolved into a fabric architecture that allows multiple hosts to access shared memory pools, significantly reducing idle memory and improving resource utilization [28][29]. - The introduction of CXL 3.0 enables peer-to-peer access to memory, which is particularly beneficial for AI workloads that require high memory bandwidth [29][33]. - Companies like Samsung and SK Hynix are developing advanced CXL-compatible memory solutions to support this vision of memory pooling [35][36]. Group 6: Future Outlook and Integration - The integration of glass substrates, UCIe, and CXL into a unified architecture is expected to define the semiconductor landscape by 2026, creating modular and flexible systems optimized for AI workloads [39][40]. - The anticipated shift towards co-packaged optics (CPO) technology will further enhance data transmission capabilities, addressing the limitations of traditional copper interconnects [44]. - The industry's focus is shifting towards a broader range of technologies, including photonics and open standards, to overcome the limitations of traditional scaling methods [46][47].

Summary of Semiconductor Advanced Packaging Industry Conference Call Industry Overview - The advanced packaging industry has become a key path to surpass Moore's Law, addressing physical bottlenecks such as high leakage power, exponential cost increases, and signal transmission losses in processes below 7nm [1][2][3] Core Technologies and Their Applications - **CoWoS-S**: Utilizes silicon interposer and TSV for high-performance interconnection, primarily used in flagship AI chips like NVIDIA H100/A100 and AMD MI300, but at a high cost [1][6] - **CoWoS-L**: Balances performance and cost through local interconnects, currently accounting for about 60% of TSMC's 2.5D packaging for Intel, and is the direction for future large AI chips and domestic companies like Huawei and Cambricon [1][6] - **CoPoS**: Replaces circular silicon interposer with rectangular panels, potentially increasing material utilization from 70%-75% to 100%. TSMC plans to trial production in 2026 and mass production in 2027, while domestic firms are in the research and prototyping phase [1][7] - **CoWoP**: Aims to eliminate the expensive substrate step by directly mounting chips onto PCBs, but is still in conceptual research due to engineering constraints [1][7] Industry Dynamics and Constraints - The necessity for advanced packaging arises from three main constraints: 1. **Physical Limits**: Quantum tunneling effects lead to significant leakage power increases as processes advance below 7nm and 5nm, making further miniaturization less cost-effective [2][3] 2. **Cost Constraints**: Increased complexity in processes raises overall costs exponentially due to more equipment, materials, and mask layers [2][3] 3. **Performance Bottlenecks**: Longer data and current transmission paths within chips lead to higher losses, hindering effective computational power release [2][3] Global and Domestic Players - Major global players in advanced packaging include TSMC, Intel, and Samsung, with OSAT firms like ASE also advancing their capabilities. Domestic firms like Changdian Technology are also positioning themselves in this space [4] Differences Between 2.5D and 3D Packaging - **2.5D Packaging**: Focuses on horizontal integration with multiple chips placed side by side on a silicon interposer, exemplified by CoWoS [5] - **3D Packaging**: Involves vertical stacking of chips, allowing for higher interconnection density and bandwidth, typically seen in HBM stacks [5] CoWoS Variants and Their Characteristics - **CoWoS-S**: High performance but high cost, used in flagship AI chips [6] - **CoWoS-R**: Uses organic RDL for flexibility and lower costs, suitable for cost-sensitive applications [6] - **CoWoS-L**: Aims for a balance between performance, cost, and size, suitable for future large AI chips [6] Future Trends and Directions - The penetration of CoWoS-L is expected to increase as domestic AI chip manufacturers like Huawei and Cambricon transition from CoWoS-S to CoWoS-L as their production volumes rise [6]

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has applied for IPO on the Shanghai Stock Exchange's Sci-Tech Innovation Board, aiming to raise 4.8 billion RMB, and is recognized as a leading advanced packaging and testing enterprise in the integrated circuit industry [1]. Group 1: Company Overview - Shenghe Jingwei specializes in advanced packaging and testing services, focusing on wafer-level packaging (WLP) and chiplet multi-chip integration packaging, particularly for high-performance chips like GPUs, CPUs, and AI chips [1][3]. - The company has established itself as one of the earliest and largest players in the chiplet multi-chip integration packaging sector in mainland China, with capabilities to compete with global leaders [1][3]. Group 2: Technological Advancements - In the mid-sized silicon wafer processing field, Shenghe Jingwei is one of the first companies in mainland China to achieve mass production of 12-inch bumping and is the first to offer 14nm advanced process bumping services, filling a gap in the high-end integrated circuit manufacturing supply chain [2]. - The company has achieved significant advancements in wafer-level chip packaging, including the development of 12-inch WLCSP and Low-K WLCSP, leading the market with a 31% share in 2024 [2]. Group 3: Market Position - In the chiplet multi-chip integration packaging domain, Shenghe Jingwei holds a dominant position with an 85% market share in 2.5D integration revenue in 2024, showcasing its advanced technology comparable to global leaders [3]. - The company provides customized advanced packaging services for various high-performance chips, catering to sectors such as AI, data centers, autonomous driving, and 5G communications, thus contributing to China's digital and intelligent infrastructure [3]. Group 4: Financial Performance - The company reported revenues of approximately 1.633 billion RMB, 3.038 billion RMB, and 4.705 billion RMB for the years 2022, 2023, and 2024 respectively, with a projected revenue of 3.178 billion RMB for the first half of 2025 [4]. - Net profits for the same periods were approximately -329 million RMB, 34.13 million RMB, 214 million RMB, and 435 million RMB for the first half of 2025 [4].

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has received approval for its IPO application on the Sci-Tech Innovation Board, meeting all necessary issuance, listing, and information disclosure requirements [1] Group 1: Company Overview - Shenghe Jingwei is a leading global advanced packaging and testing enterprise for integrated circuits, specializing in advanced 12-inch silicon wafer processing and providing a full range of advanced packaging services [5] - The company focuses on supporting high-performance chips, particularly GPUs, CPUs, and AI chips, utilizing heterogeneous integration methods to enhance performance in terms of computing power, bandwidth, and energy efficiency [5] Group 2: Market Position and Growth - According to Gartner, Shenghe Jingwei is projected to be the 10th largest and the 4th largest packaging enterprise in China by revenue in 2024, with the highest compound annual growth rate among the top ten companies from 2022 to 2024 [5] - The company is the largest provider of 12-inch Bumping capacity in mainland China and ranks first in revenue for 12-inch WLCSP and 2.5D packaging in 2024 [6] Group 3: Financial Performance - Shenghe Jingwei's revenue for the years 2022, 2023, 2024, and the first half of 2025 is approximately 1.633 billion, 3.038 billion, 4.705 billion, and 3.178 billion RMB respectively, indicating rapid growth [6] - The net profit figures for the same periods are approximately -329 million, 34.13 million, 214 million, and 43.5 million RMB, showing a turnaround to profitability in 2023 and significant growth, with the first half of 2025's net profit exceeding the total for 2024 by more than double [6] Group 4: IPO Details - The company aims to raise 4.8 billion RMB through its IPO, with the funds primarily allocated to projects related to three-dimensional multi-chip integrated packaging and ultra-high-density interconnection three-dimensional multi-chip integrated packaging [6]

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has responded to the second round of IPO inquiry from the Sci-Tech Innovation Board, with CICC as the sponsor [2] Group 1: Company Structure and Shareholding - The company has no actual controller, and major shareholders holding more than 5% of shares, including Advpackaging, have committed to a 36-month lock-up period starting from the listing date, with a total lock-up ratio of 39.22% [2] - There are interconnections among several shareholders, such as Puhua Chuangyu, Puhua Zhixin, and Hua Capital, which can be traced back to three natural person shareholders: Liu Yue, Chen Datong, and Wu Haibin [2] Group 2: Board and Management Relationships - The board consists of 9 directors, with some directors having relationships with shareholders, including being appointed by relevant shareholders or holding more than 5% equity in related shareholders [4] - The company has confirmed that there are no undisclosed relationships between senior management and shareholders, aside from those already disclosed [4] Group 3: Director Backgrounds - The company provided a detailed table of directors and their relationships with shareholders, indicating various levels of involvement and shareholdings [5] - Notable positions include the Chairman and CEO, who holds 18.14% of the equity in the employee stock ownership platform, and other directors with similar ties to shareholder entities [5] Group 4: Business Overview - Shenghe Jingwei is an advanced packaging and testing enterprise in the integrated circuit industry, focusing on 12-inch silicon wafer processing and providing advanced packaging services such as wafer-level packaging (WLP) and multi-chip integration packaging [2] - The company aims to support high-performance chips, particularly GPUs, CPUs, and AI chips, by enhancing performance through heterogeneous integration beyond Moore's Law, achieving high computing power, high bandwidth, and low power consumption [2]

Group 1 - The report emphasizes that advanced packaging is crucial for enhancing chip performance and reliability, especially in the context of the AI wave driving demand for higher integration and performance in semiconductors [8][21][25] - The semiconductor packaging and testing industry in China is expected to grow significantly, with the market size projected to reach 438.98 billion yuan by 2029, reflecting a compound annual growth rate (CAGR) of 5.8% from 2024 to 2029 [28][29] - Advanced packaging is anticipated to account for 50% of the semiconductor packaging market by 2029, with a CAGR of 10.6%, outpacing traditional packaging growth [28][29] Group 2 - The report highlights the rise of independent third-party testing services in the semiconductor industry, driven by the increasing number of IC design companies and the growing demand for testing services [42][43] - The competitive landscape for wafer testing is relatively concentrated due to high technical and investment barriers, with fewer participants compared to finished chip testing [42][43] - The report notes that independent third-party testing firms often collaborate with integrated packaging and testing companies, outsourcing wafer testing while also competing in finished chip testing [42][43]

Core Viewpoint - NVIDIA and Synopsys have announced a landmark strategic partnership involving a $2 billion investment from NVIDIA to integrate GPU-accelerated computing with Synopsys' leading EDA and semiconductor IP products, aiming to significantly accelerate chip design cycles and reduce power consumption [1][2]. Group 1: Partnership Details - The collaboration aims to create a unified cloud-native design environment that integrates Synopsys' tools with NVIDIA's computing platforms, enabling chip designers to run full-chip layout, design rule checks, and electromagnetic simulations at speeds 10 to 50 times faster than traditional CPU-based processes [1][2]. - The partnership includes the development of "Synopsys.ai Copilot," an AI-driven EDA suite that leverages NVIDIA's technology to optimize design layouts and automate testing platform generation [2][3]. Group 2: Technological Innovations - Integration of NVIDIA's cuPPA tool into Synopsys PrimePower will allow for precise dynamic power simulation across multi-chip systems, crucial for next-generation AI accelerators and autonomous vehicle SoCs [3]. - An open "NVIDIA-Synopsys foundry design kit" will provide pre-validated reference flows for TSMC's 2nm and Intel's 18A process nodes, lowering the design complexity for startups and large enterprises [3]. Group 3: Market Impact - Analysts view this partnership as a strategic defense for NVIDIA, reinforcing its competitive edge in AI training hardware by securing collaboration with Synopsys, which holds over 55% market share in the EDA sector [3]. - The agreement includes a clause requiring chips designed using their joint processes to include an NVIDIA "design watermark," which has raised concerns about potential implications for future foundry operations [4]. Group 4: Broader Applications - The partnership extends beyond semiconductors, aiming to address engineering challenges across various industries, including aerospace and automotive, by leveraging NVIDIA's AI capabilities and Synopsys' engineering solutions [5][6]. - Both companies plan to enable cloud-ready solutions for GPU-accelerated engineering, making advanced design capabilities accessible to engineering teams of all sizes [6][7].

Investment Rating - The report rates the advanced packaging industry as "stronger than the market" [1] Core Viewpoints - The advanced packaging technology is positioned as a key path to overcome the limitations of Moore's Law, driven by the exponential growth in computing power required for AI and large model training [2][14] - The global advanced packaging market is projected to exceed $79 billion by 2030, highlighting its role as a core growth engine in the semiconductor industry [2][23] - The demand for advanced packaging is surging due to the increasing need for high-performance AI chips, with TSMC's CoWoS technology becoming a critical support process for high-performance AI chips [2][17] Summary by Sections Chapter 1: Growing Demand for Intelligent Computing - The demand for intelligent computing is rapidly increasing, with significant growth in enterprise-level markets [5][9] - China's intelligent computing scale is expected to reach 725.3 EFLOPS in 2024, a year-on-year increase of 74.1% [9][10] Chapter 2: Diverse Packaging Paths - Advanced packaging technologies are evolving rapidly, with a focus on 2.5D/3D packaging solutions that are gaining popularity [2][18] - The global advanced packaging market is expected to grow from $46.1 billion in 2024 to $79.1 billion by 2030, with a compound annual growth rate (CAGR) of 21.71% for 2.5D/3D packaging [23][24] Chapter 3: Investment Recommendations - The report suggests focusing on key players in the advanced packaging sector, such as Changdian Technology, Tongfu Microelectronics, and JCET [2][24]

Core Viewpoint - The company, Shenghe Jingwei, has received approval for its IPO application on the Sci-Tech Innovation Board, aiming to raise 4.8 billion yuan for advanced packaging projects related to multi-chip integration technology [1][4]. Financial Performance - The company reported revenues of approximately 1.633 billion yuan in 2022, 3.038 billion yuan in 2023, and projected revenues of 4.705 billion yuan in 2024, with a net profit of -329 million yuan in 2022, 34.13 million yuan in 2023, and 214 million yuan in 2024 [2]. - The compound annual growth rate (CAGR) of the company's revenue from 2022 to 2024 is the highest among the top ten global packaging and testing companies [2]. Market Position - Shenghe Jingwei is ranked as the tenth largest packaging and testing company globally and the fourth largest domestically, with a leading position in various service areas within mainland China [2]. - The company holds the largest market share in 12-inch WLCSP revenue in mainland China, approximately 31% [2]. Technology and Innovation - The company has established a comprehensive technology platform for multi-chip integration packaging, particularly excelling in 2.5D integration technology, where it ranks first in revenue in mainland China with an 85% market share [3]. - Globally, the company holds an 8% market share in the 2.5D sector, competing with major players like TSMC, Intel, and Samsung [3]. Strategic Goals - The IPO aims to expand production capacity to meet the growing demand for high-performance chips, which are crucial for China's digital economy and AI development [4]. - The company plans to enhance its manufacturing and management systems, focusing on quality control and comprehensive service capabilities in advanced packaging [5].

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has received acceptance for its IPO on the Sci-Tech Innovation Board, indicating a significant step in its growth trajectory in the semiconductor industry [3]. Company Overview - Shenghe Jingwei is an advanced packaging and testing enterprise for integrated circuits, focusing on 12-inch silicon wafer processing and providing wafer-level packaging (WLP) and multi-chip integration packaging services [3]. - The company aims to support high-performance chips, particularly GPUs, CPUs, and AI chips, through heterogeneous integration methods that enhance performance metrics such as computing power, bandwidth, and energy efficiency [3]. Financial Performance - The company reported revenues of 1.633 billion yuan, 3.038 billion yuan, and 4.705 billion yuan for the years 2022, 2023, and 2024 respectively, with a projected revenue of 3.178 billion yuan for the first half of 2025 [3]. - Net profits for the same periods were -329 million yuan, 34.13 million yuan, 214 million yuan, and 43.5 million yuan for the first half of 2025 [3]. Market Position - According to Gartner, Shenghe Jingwei is projected to be the 10th largest packaging and testing company globally and the 4th largest domestically by 2024, with the highest compound annual growth rate in revenue among the top ten companies from 2022 to 2024 [3]. Shareholding Structure - As of the date of the prospectus, the largest shareholder is Wuxi Chanfang Fund with a 10.89% stake, followed by a group of shareholders from the China Merchants Bank system with a combined 9.95% [4]. - The company has no controlling shareholder or actual controller, ensuring a dispersed shareholding structure where no single shareholder can dominate the shareholder meetings [5].