公众号记得加星标⭐️，第一时间看推送不会错过。 AMD之所以面临更高的发热量和更低的每瓦性能，原因很简单：Zen 5及其所有前代产品都是为数据 中心市场而设计的。知情工程师不断向我们透露，Infinity Fabric架构在移动领域功耗过高，难以实 现高效设计。此外，AMD也缺乏强有力的小核心策略。 福雷斯特·诺罗德领导的数据中心团队之所以能够蓬勃发展，得益于以数据中心为先导、覆盖面广且 功能强大的核心战略。而消费者和商业移动业务部门则不得不接受 Zen 5 的不足之处。 4nm工艺很难与英特尔18A和台积电3nm工艺竞争。 上周，AMD向金融和行业分析师展示了其未来几年的人工智能、数据中心和消费级产品计划。尽管 在数据中心市场取得了巨大成功，人工智能领域也取得了一定的进展，并且未来发展路线图清晰明 确，但我仍想指出其消费级产品路线图的一个不足之处，尤其是在2026年方面。 计算与图形事业部高级副总裁兼总经理Jack Huynh及其团队正朝着正确的方向前进；X3D台式机的 成功对微软来说是一项重大胜利。然而，在消费业务的某些关键领域，尤其是在消费级和商用笔记本 电脑领域，不太可能在2026年就立即取得成功。公 ...

Core Insights - Intel's latest high-performance CPU architecture, Lion Cove, shows significant improvements over its predecessor, Raptor Cove, particularly in instruction cycles and execution engine organization [1] - Lion Cove's performance on the Arrow Lake desktop platform is competitive with AMD's Zen 5 architecture, achieving better overall performance at lower power consumption compared to Raptor Cove [1] - Gaming performance, which is a key focus for many users, varies significantly from productivity workloads, highlighting the need for tailored optimizations [1] Performance Analysis - Lion Cove supports up to 8 micro-operations per cycle, translating to approximately 8 instructions per cycle, with high IPC results in SPEC CPU2017 tests, some exceeding 4 IPC [5] - Despite high IPC capabilities, gaming workloads typically operate at the lower end of the IPC spectrum, with performance limited by front-end and back-end latencies [5][11] - The architecture features a four-level data cache setup, with L1 data cache divided into two levels, enhancing performance by alleviating L2 cache load [13][15] Memory Access and Latency - Accessing L3 and DRAM incurs high latency costs, with performance monitoring events indicating how each cache level impacts overall performance [17][19] - Lion Cove's L1.5 cache helps mitigate some L1 cache miss issues, although its absolute hit rate remains modest [15] - The architecture's memory access patterns reveal that while L2 cache misses are rare, the high costs associated with L3 or DRAM accesses can still significantly affect performance [19] Front-End and Back-End Performance - The front-end of Lion Cove experiences some throughput losses, primarily due to instruction fetch delays and branch prediction errors [27][30] - The architecture's branch predictor performs well, but recovery from prediction errors can lead to significant delays, impacting overall performance [30][39] - Lion Cove can exit up to 12 micro-operations per cycle, with average execution reaching 28 micro-operations before encountering blockages [44] Comparative Analysis - Compared to AMD's Zen 4, Lion Cove faces more severe back-end memory latency issues, while its front-end latency challenges are less pronounced [45] - The architecture's larger BTB and instruction cache help prevent code fetches from slower caches, contributing positively to performance [46] - The differences in design strategies between Intel and AMD highlight the ongoing optimization challenges faced by both companies in meeting diverse workload demands [47]