Core Insights - Intel's latest high-performance CPU architecture, Lion Cove, shows significant improvements over its predecessor, Raptor Cove, particularly in instruction cycles and execution engine organization [1] - Lion Cove's performance on the Arrow Lake desktop platform is competitive with AMD's Zen 5 architecture, achieving better overall performance at lower power consumption compared to Raptor Cove [1] - Gaming performance, which is a key focus for many users, varies significantly from productivity workloads, highlighting the need for tailored optimizations [1] Performance Analysis - Lion Cove supports up to 8 micro-operations per cycle, translating to approximately 8 instructions per cycle, with high IPC results in SPEC CPU2017 tests, some exceeding 4 IPC [5] - Despite high IPC capabilities, gaming workloads typically operate at the lower end of the IPC spectrum, with performance limited by front-end and back-end latencies [5][11] - The architecture features a four-level data cache setup, with L1 data cache divided into two levels, enhancing performance by alleviating L2 cache load [13][15] Memory Access and Latency - Accessing L3 and DRAM incurs high latency costs, with performance monitoring events indicating how each cache level impacts overall performance [17][19] - Lion Cove's L1.5 cache helps mitigate some L1 cache miss issues, although its absolute hit rate remains modest [15] - The architecture's memory access patterns reveal that while L2 cache misses are rare, the high costs associated with L3 or DRAM accesses can still significantly affect performance [19] Front-End and Back-End Performance - The front-end of Lion Cove experiences some throughput losses, primarily due to instruction fetch delays and branch prediction errors [27][30] - The architecture's branch predictor performs well, but recovery from prediction errors can lead to significant delays, impacting overall performance [30][39] - Lion Cove can exit up to 12 micro-operations per cycle, with average execution reaching 28 micro-operations before encountering blockages [44] Comparative Analysis - Compared to AMD's Zen 4, Lion Cove faces more severe back-end memory latency issues, while its front-end latency challenges are less pronounced [45] - The architecture's larger BTB and instruction cache help prevent code fetches from slower caches, contributing positively to performance [46] - The differences in design strategies between Intel and AMD highlight the ongoing optimization challenges faced by both companies in meeting diverse workload demands [47]

最近些年。RISC-V引起了全球关注。这款革命性的 ISA 凭借其持续的创新，以及无数的学习 和工具资源以及来自工程界的贡献，像潮水般席卷了市场。RISC-V 最大的魅力在于它是一款 开源 ISA。 在本文中，我（指代本文作者Mitu Raj，下同）将介绍如何从零开始设计一款RISC-V CPU ，我们将讲解定义规格、设计和改进架构、识别和解决挑战、开发 RTL、实现 CPU 以及在 仿真/FPGA 板上测试 CPU 的流程。 以下为文章正文： 从命名开始 如果您希望可以时常见面，欢迎标星收藏哦~ 为你的想法命名或打造品牌至关重要，这样才能激励你不断前进，直至达成目标！我们打算构建一 个非常简单的处理器，所以我想出了一个花哨的名字" Pequeno "，在西班牙语中是"微小"的意 思；完整名称是：Pequeno RISC-V CPU，又名PQR5。 RISC-V 的 ISA 架构有多种风格和扩展。我们先从最简单的RV32I开始，它又称为 32 位基本整数 ISA。该 ISA 适用于构建支持整数运算的 32 位 CPU。因此，Pequeno 的第一个规格如下： Pequeno 是一款 32 位 RISC-V C ...