Core Viewpoint - The article emphasizes the importance of interconnect architecture in AI infrastructure, highlighting that while GPUs are crucial, the ability to train and run large models relies heavily on effective interconnect systems [1]. Group 1: Interconnect Architecture - Interconnect architecture encompasses various levels, including chip-to-chip communication within packages and system-level networks that support thousands of accelerators [1]. - Nvidia's dominance in the industry is attributed to its expertise in developing and integrating these interconnect architectures [1]. - Broadcom has been quietly advancing various technologies related to interconnect architecture, including Ethernet architectures for large-scale expansion and internal chip interconnect technologies [1][3]. Group 2: Ethernet Switch Technology - Broadcom has introduced high-capacity switches, such as the 51.2Tbps Tomahawk 5 and the recently launched 102.4Tbps Tomahawk 6, which can significantly reduce the number of switches needed for large GPU clusters [3]. - The number of switches required decreases as the switch's port count increases, allowing for more efficient connections among GPUs [3]. - Nvidia has also announced its own 102.4Tbps Ethernet switch, indicating a competitive landscape in high-capacity switch technology [4]. Group 3: Scalable Ethernet Solutions - Broadcom's Tomahawk 6 switches are positioned as a shortcut for rack-level architectures, supporting between 8 to 72 GPUs, with future designs expected to support up to 576 GPUs by 2027 [6]. - Ethernet technology is being utilized for both scalable and large-scale networks, with Intel and AMD also planning to implement Ethernet for their systems [7]. Group 4: Co-Packaged Optics (CPO) Technology - Broadcom has invested in co-packaged optics (CPO) technology, which integrates components typically found in pluggable transceivers into the same package as the switch ASIC, significantly reducing power consumption [9][10]. - The efficiency of Broadcom's CPO technology is reported to be over 3.5 times that of traditional pluggable devices [10]. - The third generation of CPO technology is expected to support up to 512 200Gbps optical ports, with future developments aiming for 400Gbps channels by 2028 [11]. Group 5: Multi-Chip Architecture - As Moore's Law slows, the industry is shifting towards multi-chip architectures, allowing for higher yields and optimized costs by using smaller chips [14]. - Broadcom has developed a 3.5D eXtreme Dimension System in Package (3.5D XDSiP) technology to facilitate the design of multi-chip processors, which is open for licensing to other companies [15]. - The first products based on this design are expected to enter production by 2026, although the specific applications of Broadcom's technology in AI chips may remain undisclosed [15].