Core Insights - RISC-V has gained global attention due to its innovative open-source ISA, which allows for extensive contributions from the engineering community [1] - The article outlines the process of designing a RISC-V CPU from scratch, including defining specifications, designing architecture, and testing [1] Specification and Architecture - The CPU named "Pequeno" is defined as a 32-bit RISC-V CPU supporting the RV32I ISA, which includes 37 basic instructions [2][9] - The architecture is a simple single-core CPU that executes one instruction at a time in a pipelined manner, without supporting RISC-V privileged specifications [9][11] - The CPU features a classic five-stage RISC pipeline, which includes instruction fetch (IF), decode (ID), execute (EX), memory access (MEM), and write-back (WB) [17][18] Instruction Types and Implementation - The RV32I instruction set is categorized into six types: R-type, I-type, S-type, B-type, U-type, and J-type, with a total of 37 basic instructions [3][4] - An additional 13 pseudo/custom instructions were added, expanding the ISA to 50 instructions to simplify the work for assembly programmers [5] Pipeline Design - The pipeline is designed to achieve a maximum IPC (Instructions Per Cycle) of 1, which is the theoretical highest performance for a single-issue processor [11][18] - The architecture does not implement timers, interrupts, or exceptions, focusing solely on integer operations [9][11] Pipeline Hazards - Pipeline hazards are categorized into structural hazards, control hazards, and data hazards, which can disrupt the normal execution of instructions [30][32] - Structural hazards occur due to hardware resource conflicts, while control hazards arise from branch instructions that affect the flow of execution [36][39] - Data hazards can be further divided into output dependencies (WAW), anti-dependencies (WAR), and true dependencies (RAW), which can lead to incorrect execution if not managed properly [41][42] Mitigation Strategies - To mitigate structural hazards, the architecture implements separate instruction and data memory access paths and uses dual ports for the register file [35] - Control hazards are addressed through branch prediction logic, which attempts to predict the outcome of branch instructions to minimize pipeline stalls [40] - Data hazards are managed using techniques such as pipeline interlocks and data forwarding, allowing dependent instructions to access the most recent data without unnecessary stalls [56][49] Future Developments - The article indicates that future discussions will delve into the RTL design of each pipeline stage and functional unit, starting with the Fetch Unit (FU) [60]