Core Viewpoint - The article discusses the advancements in SRAM technology presented by Intel and TSMC at the IEEE International Solid-State Circuits Conference (ISSCC), highlighting the use of new nanosheet transistor architecture to improve memory density and performance. Group 1: SRAM Technology Advancements - Intel and TSMC have achieved SRAM density of 38.1 megabits per square millimeter using storage cells of 0.021 square micrometers, with Intel improving density by 23% and TSMC by 12% [1][2] - The new nanosheet transistor architecture allows for better scalability of SRAM compared to previous FinFET designs, enabling more flexible current driving capabilities [2][3] - Intel's 18a technology introduces a backside power network, which helps reduce circuit area by allowing for a critical capacitor to be built beneath the SRAM cell [3][4] Group 2: Design Flexibility and Performance - Nanosheet devices provide greater flexibility in SRAM unit size, allowing for a reduction in unit area by up to 23% for Intel [3] - TSMC engineers have extended bit line lengths to connect more SRAM units, reducing the need for peripheral circuits and increasing overall density by nearly 10% [4] - Synopsys has developed a new SRAM design that achieves similar density to Intel and TSMC but operates at lower speeds, with a maximum speed of 2.3 GHz compared to TSMC's 4.2 GHz and Intel's 5.6 GHz [6][7] Group 3: Power Efficiency - Synopsys employs a dual-rail design that allows SRAM arrays and peripheral circuits to operate at different voltages, reducing power consumption while maintaining performance [5][6] - The voltage for SRAM cells can range from 540 millivolts to 1.4 volts, while peripheral voltage can be as low as 380 millivolts, optimizing power efficiency [6]