Core Viewpoint - Applied Materials has developed an advanced copper interconnect process for logic chips at 2nm and beyond, addressing challenges in performance and reliability due to shrinking interconnect sizes [2][23]. Group 1: Advanced Logic Chip Development - The new copper interconnect process utilizes Low k dielectric materials and RuCo liner technology, demonstrating feasibility through AI accelerator test chips based on the latest 2nm transistor technology [2][23]. - The complexity of interconnects in advanced chips, which can contain billions of transistors, has led to increased resistance and other issues affecting chip performance and reliability [2][23]. - The need for process innovation to reduce resistance and capacitance without compromising reliability and yield is emphasized by industry experts [2][23]. Group 2: Semiconductor Industry Background - The semiconductor industry produces various types of chips, including processors, GPUs, and memory chips, which are essential for numerous electronic systems [3]. - Chips are manufactured in large factories known as fabs, where complex electronic circuits are integrated into silicon wafers [3]. Group 3: Evolution of Transistors and Interconnects - The history of semiconductor technology dates back to the invention of the transistor in 1947, leading to the development of integrated circuits in the late 1950s [7][10]. - The transition from aluminum to copper interconnects in the 1990s significantly improved chip performance due to copper's lower resistivity [11][12]. Group 4: Challenges and Innovations in Interconnect Technology - As technology advances to 20nm and below, copper interconnects face challenges such as RC delay, which affects chip speed [17][18]. - The introduction of FinFET transistors and the shift to cobalt liners have helped mitigate some of these challenges, allowing for the development of chips at 3nm nodes [18][20]. - The industry is moving towards GAA (Gate-All-Around) transistors for 2nm nodes, which promise better performance but come with increased manufacturing complexity and costs [20][23]. Group 5: Applied Materials' Copper Interconnect Process - The copper interconnect process developed by Applied Materials involves several steps, including dielectric deposition, metal filling, annealing, and chemical mechanical polishing (CMP) [25][29]. - The use of RuCo liners and TaN barriers in the process allows for reduced resistance and improved performance, with a reported performance enhancement of 2.5% in a 2nm test chip [24][25]. - The integration of back-side power delivery networks (BSPDN) in advanced nodes aims to address power distribution challenges while maintaining signal integrity [32][35].

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容编译自IEEE，谢谢。 上周，在IEEE 国际固态电路会议 (ISSCC) 上，先进芯片制造领域的两大竞争对手英特尔和台积电详 细介绍了使用其最新技术英特尔 18z和台积电 N2构建的关键存储器电路SRAM的功能。多年来，芯 片制造商不断缩小电路尺寸的能力已经放缓——但缩小由大量存储单元和支持电路组成的SRAM尤其 困难。 柔性晶体管可制造更小、更好的 SRAM SRAM 单元在六晶体管电路中存储一个位。但这些晶体管并不完全相同，因为它们对晶体管有不同 的要求。在基于 FinFET 的单元中，这可能意味着构建两对各有两个鳍片的器件，其余两个晶体管各 有一个鳍片。 台积电高级总监兼 IEEE 院士张宗勇(Tsung-Yung Jonathan Chang)表示，纳米片器件"在 SRAM 单 元尺寸方面提供了更大的灵活性"。晶体管之间的意外差异较少他表示，纳米片的品质可以提高 SRAM 的低压性能。 这两家公司最密集的 SRAM 块提供 38.1 兆比特/平方毫米，使用的存储单元为 0.021 平方微米。英 特尔的密度提高了 23% ，台积电提高了 12% 。有 ...