Group 1 - Hybrid Bonding (HB) technology is commonly used among 3D NAND manufacturers such as Yangtze Memory Technologies Corp (YMTC), KIOXIA, and Western Digital, with YMTC branding it as Xtacking and KIOXIA/Western Digital referring to it as CBA [1] - The benefits of HB technology include significant improvements in storage density and higher I/O speeds, with major manufacturers like Micron, Samsung, and SK Hynix transitioning to HB structures for their NAND devices [2] - Future applications of HB technology may extend to DRAM scaling, including hybrid bonding 3D DRAM and advanced High Bandwidth Memory (HBM) devices [2] Group 2 - HBM DRAM stacking must reduce composite chip module height to meet overall packaging size goals, with JEDEC standards dictating HBM module height at 720µm for HBM3 and 775µm for HBM3E and beyond [3] - The thickness of HBM DRAM chip cores is currently 55µm for HBM3 devices, with AMD's new 12-chip stacked HBM3 device having a reduced core thickness of 37µm to comply with JEDEC standards [8] - Future HBM modules may achieve 16-stack, 20-stack, or even 24-stack configurations with a chip thickness of 20µm using hybrid bonding interconnects, although challenges remain in scaling due to cost, defects, and thermal management [8]