Group 1 - Hybrid Bonding (HB) technology is commonly used among 3D NAND manufacturers such as Yangtze Memory Technologies Corp (YMTC), KIOXIA, and Western Digital, with YMTC branding it as Xtacking and KIOXIA/Western Digital referring to it as CBA [1] - The benefits of HB technology include significant improvements in storage density and higher I/O speeds, with major manufacturers like Micron, Samsung, and SK Hynix transitioning to HB structures for their NAND devices [2] - Future applications of HB technology may extend to DRAM scaling, including hybrid bonding 3D DRAM and advanced High Bandwidth Memory (HBM) devices [2] Group 2 - HBM DRAM stacking must reduce composite chip module height to meet overall packaging size goals, with JEDEC standards dictating HBM module height at 720µm for HBM3 and 775µm for HBM3E and beyond [3] - The thickness of HBM DRAM chip cores is currently 55µm for HBM3 devices, with AMD's new 12-chip stacked HBM3 device having a reduced core thickness of 37µm to comply with JEDEC standards [8] - Future HBM modules may achieve 16-stack, 20-stack, or even 24-stack configurations with a chip thickness of 20µm using hybrid bonding interconnects, although challenges remain in scaling due to cost, defects, and thermal management [8]

Core Viewpoint - SMIC reported a revenue of approximately 32 billion RMB for the first half of the year, which is significantly lower than TSMC's 425.8 billion RMB, highlighting a 12-fold revenue gap attributed to the lack of advanced EUV lithography machines [1][3][5]. Group 1: Revenue Comparison - SMIC's revenue of 32 billion RMB is substantial but pales in comparison to TSMC's 425.8 billion RMB, indicating a significant disparity in earnings [1][3]. - The 12-fold difference in revenue is primarily due to the advanced EUV lithography technology that TSMC possesses, which is crucial for manufacturing high-end chips [3][5]. Group 2: Technology and Supply Chain Challenges - The inability to acquire EUV lithography machines, due to international agreements like the Wassenaar Arrangement and the US-Japan-Netherlands pact, restricts SMIC to producing only mature process chips (14nm and above) [5][9]. - EUV lithography machines are complex systems requiring contributions from multiple countries, making it difficult for any single nation to produce them independently [5][7]. Group 3: Future Prospects and Strategies - Despite current limitations, SMIC and other Chinese companies are aggressively expanding in the mature process segment, aiming to dominate this market by 2030 [9][10]. - The industry is exploring alternative technologies, such as DUV lithography and chip stacking, to produce competitive 7nm chips, as demonstrated by Huawei's Kirin 9000S and 9010 chips [10][12]. - A fully domestic chip supply chain is being established, with advancements in design software, chip design, manufacturing, and packaging, indicating a strong foundation for future growth [12][14].